aboutsummaryrefslogtreecommitdiff
path: root/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs
diff options
context:
space:
mode:
Diffstat (limited to 'src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs')
-rw-r--r--src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs47
1 files changed, 25 insertions, 22 deletions
diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs
index 40312f4a..006c14b5 100644
--- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs
+++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs
@@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using System.Numerics;
-
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -48,7 +47,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
AtomsSize.S32 => AtomSize.S32,
AtomsSize.U64 => AtomSize.U64,
AtomsSize.S64 => AtomSize.S64,
- _ => AtomSize.U32
+ _ => AtomSize.U32,
};
Operand id = Const(context.Config.ResourceManager.SharedMemoryId);
@@ -85,7 +84,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
for (int index = 0; index < count; index++)
{
- Register dest = new Register(op.Dest + index, RegisterType.Gpr);
+ Register dest = new(op.Dest + index, RegisterType.Gpr);
if (dest.IsRZ)
{
@@ -309,14 +308,14 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
LsSize2.B64 => 2,
LsSize2.B128 => 4,
- _ => 1
+ _ => 1,
};
Operand baseOffset = context.Copy(srcA);
for (int index = 0; index < count; index++)
{
- Register dest = new Register(rd + index, RegisterType.Gpr);
+ Register dest = new(rd + index, RegisterType.Gpr);
if (dest.IsRZ)
{
@@ -354,7 +353,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
for (int index = 0; index < count; index++)
{
- Register dest = new Register(rd + index, RegisterType.Gpr);
+ Register dest = new(rd + index, RegisterType.Gpr);
if (dest.IsRZ)
{
@@ -390,7 +389,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
LsSize2.B64 => 2,
LsSize2.B128 => 4,
- _ => 1
+ _ => 1,
};
Operand baseOffset = context.Copy(srcA);
@@ -476,22 +475,18 @@ namespace Ryujinx.Graphics.Shader.Instructions
LsSize.S8 => StorageKind.GlobalMemoryS8,
LsSize.U16 => StorageKind.GlobalMemoryU16,
LsSize.S16 => StorageKind.GlobalMemoryS16,
- _ => StorageKind.GlobalMemory
+ _ => StorageKind.GlobalMemory,
};
}
private static int GetVectorCount(LsSize size)
{
- switch (size)
+ return size switch
{
- case LsSize.B64:
- return 2;
- case LsSize.B128:
- case LsSize.UB128:
- return 4;
- }
-
- return 1;
+ LsSize.B64 => 2,
+ LsSize.B128 or LsSize.UB128 => 4,
+ _ => 1,
+ };
}
private static (Operand, Operand) Get40BitsAddress(
@@ -544,10 +539,18 @@ namespace Ryujinx.Graphics.Shader.Instructions
switch (size)
{
- case LsSize.U8: value = ZeroExtendTo32(context, value, 8); break;
- case LsSize.U16: value = ZeroExtendTo32(context, value, 16); break;
- case LsSize.S8: value = SignExtendTo32(context, value, 8); break;
- case LsSize.S16: value = SignExtendTo32(context, value, 16); break;
+ case LsSize.U8:
+ value = ZeroExtendTo32(context, value, 8);
+ break;
+ case LsSize.U16:
+ value = ZeroExtendTo32(context, value, 16);
+ break;
+ case LsSize.S8:
+ value = SignExtendTo32(context, value, 8);
+ break;
+ case LsSize.S16:
+ value = SignExtendTo32(context, value, 16);
+ break;
}
return value;
@@ -578,4 +581,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return value;
}
}
-} \ No newline at end of file
+}