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Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs71
1 files changed, 34 insertions, 37 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
index 45481f85..e7fad89f 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
@@ -13,33 +13,30 @@ namespace Ryujinx.Tests.Cpu
#region "ValueSource (Types)"
private static ulong[] _1D_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _2S_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _4H_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _8B_()
{
- return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
}
#endregion
#region "ValueSource (Opcodes)"
private static uint[] _Vshr_Imm_SU8_()
{
- return new uint[]
+ return new[]
{
0xf2880010u, // VSHR.S8 D0, D0, #8
0xf2880110u, // VSRA.S8 D0, D0, #8
@@ -50,7 +47,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Vshr_Imm_SU16_()
{
- return new uint[]
+ return new[]
{
0xf2900010u, // VSHR.S16 D0, D0, #16
0xf2900110u, // VSRA.S16 D0, D0, #16
@@ -61,7 +58,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Vshr_Imm_SU32_()
{
- return new uint[]
+ return new[]
{
0xf2a00010u, // VSHR.S32 D0, D0, #32
0xf2a00110u, // VSRA.S32 D0, D0, #32
@@ -72,7 +69,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Vshr_Imm_SU64_()
{
- return new uint[]
+ return new[]
{
0xf2800190u, // VSRA.S64 D0, D0, #64
0xf2800290u, // VRSHR.S64 D0, D0, #64
@@ -82,7 +79,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Vqshrn_Vqrshrn_Vrshrn_Imm_()
{
- return new uint[]
+ return new[]
{
0xf2800910u, // VORR.I16 D0, #0 (immediate value changes it into QSHRN)
0xf2800950u, // VORR.I16 Q0, #0 (immediate value changes it into QRSHRN)
@@ -92,7 +89,7 @@ namespace Ryujinx.Tests.Cpu
private static uint[] _Vqshrun_Vqrshrun_Imm_()
{
- return new uint[]
+ return new[]
{
0xf3800810u, // VMOV.I16 D0, #0x80 (immediate value changes it into QSHRUN)
0xf3800850u // VMOV.I16 Q0, #0x80 (immediate value changes it into QRSHRUN)
@@ -104,12 +101,12 @@ namespace Ryujinx.Tests.Cpu
private const int RndCntShiftImm = 2;
[Test, Pairwise]
- public void Vshr_Imm_SU8([ValueSource("_Vshr_Imm_SU8_")] uint opcode,
+ public void Vshr_Imm_SU8([ValueSource(nameof(_Vshr_Imm_SU8_))] uint opcode,
[Range(0u, 3u)] uint rd,
[Range(0u, 3u)] uint rm,
- [ValueSource("_8B_")] [Random(RndCnt)] ulong z,
- [ValueSource("_8B_")] [Random(RndCnt)] ulong b,
- [Values(1u, 8u)] [Random(2u, 7u, RndCntShiftImm)] uint shiftImm,
+ [ValueSource(nameof(_8B_))] ulong z,
+ [ValueSource(nameof(_8B_))] ulong b,
+ [Values(1u, 8u)] uint shiftImm,
[Values] bool u,
[Values] bool q)
{
@@ -119,12 +116,12 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Vshr_Imm_SU16([ValueSource("_Vshr_Imm_SU16_")] uint opcode,
+ public void Vshr_Imm_SU16([ValueSource(nameof(_Vshr_Imm_SU16_))] uint opcode,
[Range(0u, 3u)] uint rd,
[Range(0u, 3u)] uint rm,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong z,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong b,
- [Values(1u, 16u)] [Random(2u, 15u, RndCntShiftImm)] uint shiftImm,
+ [ValueSource(nameof(_4H_))] ulong z,
+ [ValueSource(nameof(_4H_))] ulong b,
+ [Values(1u, 16u)] uint shiftImm,
[Values] bool u,
[Values] bool q)
{
@@ -134,12 +131,12 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Vshr_Imm_SU32([ValueSource("_Vshr_Imm_SU32_")] uint opcode,
+ public void Vshr_Imm_SU32([ValueSource(nameof(_Vshr_Imm_SU32_))] uint opcode,
[Range(0u, 3u)] uint rd,
[Range(0u, 3u)] uint rm,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong z,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong b,
- [Values(1u, 32u)] [Random(2u, 31u, RndCntShiftImm)] uint shiftImm,
+ [ValueSource(nameof(_2S_))] ulong z,
+ [ValueSource(nameof(_2S_))] ulong b,
+ [Values(1u, 32u)] uint shiftImm,
[Values] bool u,
[Values] bool q)
{
@@ -149,12 +146,12 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Vshr_Imm_SU64([ValueSource("_Vshr_Imm_SU64_")] uint opcode,
+ public void Vshr_Imm_SU64([ValueSource(nameof(_Vshr_Imm_SU64_))] uint opcode,
[Range(0u, 3u)] uint rd,
[Range(0u, 3u)] uint rm,
- [ValueSource("_1D_")] [Random(RndCnt)] ulong z,
- [ValueSource("_1D_")] [Random(RndCnt)] ulong b,
- [Values(1u, 64u)] [Random(2u, 63u, RndCntShiftImm)] uint shiftImm,
+ [ValueSource(nameof(_1D_))] ulong z,
+ [ValueSource(nameof(_1D_))] ulong b,
+ [Values(1u, 64u)] uint shiftImm,
[Values] bool u,
[Values] bool q)
{
@@ -195,7 +192,7 @@ namespace Ryujinx.Tests.Cpu
public void Vshl_Imm([Values(0u)] uint rd,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u, 3u)] uint size,
- [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
+ [Random(RndCntShiftImm)] uint shiftImm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
@@ -229,7 +226,7 @@ namespace Ryujinx.Tests.Cpu
public void Vshrn_Imm([Values(0u, 1u)] uint rd,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
- [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
+ [Random(RndCntShiftImm)] uint shiftImm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b)
@@ -253,11 +250,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Vqshrn_Vqrshrn_Vrshrn_Imm([ValueSource("_Vqshrn_Vqrshrn_Vrshrn_Imm_")] uint opcode,
+ public void Vqshrn_Vqrshrn_Vrshrn_Imm([ValueSource(nameof(_Vqshrn_Vqrshrn_Vrshrn_Imm_))] uint opcode,
[Values(0u, 1u)] uint rd,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
- [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
+ [Random(RndCntShiftImm)] uint shiftImm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
@@ -287,11 +284,11 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise]
- public void Vqshrun_Vqrshrun_Imm([ValueSource("_Vqshrun_Vqrshrun_Imm_")] uint opcode,
+ public void Vqshrun_Vqrshrun_Imm([ValueSource(nameof(_Vqshrun_Vqrshrun_Imm_))] uint opcode,
[Values(0u, 1u)] uint rd,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
- [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm,
+ [Random(RndCntShiftImm)] uint shiftImm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b)
@@ -315,4 +312,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
-}
+} \ No newline at end of file
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-03-23 02:22:54 +0000