diff options
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestBfm.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestBfm.cs | 40 |
1 files changed, 19 insertions, 21 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestBfm.cs b/Ryujinx.Tests/Cpu/CpuTestBfm.cs index 24f69036..c169ee41 100644 --- a/Ryujinx.Tests/Cpu/CpuTestBfm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestBfm.cs @@ -9,17 +9,15 @@ namespace Ryujinx.Tests.Cpu { #if Bfm private const int RndCnt = 2; - private const int RndCntImmr = 2; - private const int RndCntImms = 2; [Test, Pairwise, Description("BFM <Xd>, <Xn>, #<immr>, #<imms>")] public void Bfm_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Random(RndCnt)] ulong xd, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, + [Values(0u, 31u, 32u, 63u)] uint immr, + [Values(0u, 31u, 32u, 63u)] uint imms) { uint opcode = 0xB3400000; // BFM X0, X0, #0, #0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -37,9 +35,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Random(RndCnt)] uint wd, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms) + 0x80000000u, 0xFFFFFFFFu)] uint wn, + [Values(0u, 15u, 16u, 31u)] uint immr, + [Values(0u, 15u, 16u, 31u)] uint imms) { uint opcode = 0x33000000; // BFM W0, W0, #0, #0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -56,9 +54,9 @@ namespace Ryujinx.Tests.Cpu public void Sbfm_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, + [Values(0u, 31u, 32u, 63u)] uint immr, + [Values(0u, 31u, 32u, 63u)] uint imms) { uint opcode = 0x93400000; // SBFM X0, X0, #0, #0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -75,9 +73,9 @@ namespace Ryujinx.Tests.Cpu public void Sbfm_32bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms) + 0x80000000u, 0xFFFFFFFFu)] uint wn, + [Values(0u, 15u, 16u, 31u)] uint immr, + [Values(0u, 15u, 16u, 31u)] uint imms) { uint opcode = 0x13000000; // SBFM W0, W0, #0, #0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -94,9 +92,9 @@ namespace Ryujinx.Tests.Cpu public void Ubfm_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, + [Values(0u, 31u, 32u, 63u)] uint immr, + [Values(0u, 31u, 32u, 63u)] uint imms) { uint opcode = 0xD3400000; // UBFM X0, X0, #0, #0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -113,9 +111,9 @@ namespace Ryujinx.Tests.Cpu public void Ubfm_32bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms) + 0x80000000u, 0xFFFFFFFFu)] uint wn, + [Values(0u, 15u, 16u, 31u)] uint immr, + [Values(0u, 15u, 16u, 31u)] uint imms) { uint opcode = 0x53000000; // UBFM W0, W0, #0, #0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -129,4 +127,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -} +}
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