diff options
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestAluRs32.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestAluRs32.cs | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs index 25b2c968..d241aac4 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs @@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu #region "ValueSource (Opcodes)" private static uint[] _Add_Adds_Rsb_Rsbs_() { - return new uint[] + return new[] { 0xe0800000u, // ADD R0, R0, R0, LSL #0 0xe0900000u, // ADDS R0, R0, R0, LSL #0 @@ -23,7 +23,7 @@ namespace Ryujinx.Tests.Cpu private static uint[] _Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_() { - return new uint[] + return new[] { 0xe0a00000u, // ADC R0, R0, R0 0xe0b00000u, // ADCS R0, R0, R0 @@ -35,8 +35,6 @@ namespace Ryujinx.Tests.Cpu } #endregion - private const int RndCnt = 2; - private const int RndCntAmount = 2; [Test, Pairwise] public void Adc_Adcs_Rsc_Rscs_Sbc_Sbcs([ValueSource("_Adc_Adcs_Rsc_Rscs_Sbc_Sbcs_")] uint opcode, @@ -44,9 +42,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 13u)] uint rn, [Values(2u, 13u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values] bool carryIn) { opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); @@ -64,11 +62,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 13u)] uint rn, [Values(2u, 13u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { opcode |= ((rm & 15) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12); opcode |= ((shift & 3) << 5) | ((amount & 31) << 7); @@ -81,4 +79,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -} +}
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