diff options
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestAluRs.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestAluRs.cs | 225 |
1 files changed, 111 insertions, 114 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs index 418dd56d..20e0e396 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs @@ -8,18 +8,15 @@ namespace Ryujinx.Tests.Cpu public sealed class CpuTestAluRs : CpuTest { #if AluRs - private const int RndCnt = 2; - private const int RndCntAmount = 2; - private const int RndCntLsb = 2; [Test, Pairwise, Description("ADC <Xd>, <Xn>, <Xm>")] public void Adc_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values] bool carryIn) { uint opcode = 0x9A000000; // ADC X0, X0, X0 @@ -37,9 +34,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values] bool carryIn) { uint opcode = 0x1A000000; // ADC W0, W0, W0 @@ -57,9 +54,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values] bool carryIn) { uint opcode = 0xBA000000; // ADCS X0, X0, X0 @@ -77,9 +74,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values] bool carryIn) { uint opcode = 0x3A000000; // ADCS W0, W0, W0 @@ -97,11 +94,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0x8B000000; // ADD X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -119,11 +116,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x0B000000; // ADD W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -141,11 +138,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0xAB000000; // ADDS X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -163,11 +160,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x2B000000; // ADDS W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -185,11 +182,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0x8A000000; // AND X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -207,11 +204,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x0A000000; // AND W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -229,11 +226,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0xEA000000; // ANDS X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -251,11 +248,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x6A000000; // ANDS W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -273,9 +270,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm) { uint opcode = 0x9AC02800; // ASRV X0, X0, X0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -292,9 +289,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm) + 0x80000000u, 0xFFFFFFFFu)] uint wm) { uint opcode = 0x1AC02800; // ASRV W0, W0, W0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -311,11 +308,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0x8A200000; // BIC X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -333,11 +330,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x0A200000; // BIC W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -355,11 +352,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0xEA200000; // BICS X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -377,11 +374,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x6A200000; // BICS W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -399,11 +396,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0xCA200000; // EON X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -421,11 +418,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x4A200000; // EON W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -443,11 +440,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0xCA000000; // EOR X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -465,11 +462,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x4A000000; // EOR W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -487,10 +484,10 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntLsb)] uint lsb) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, + [Values(0u, 31u, 32u, 63u)] uint lsb) { uint opcode = 0x93C00000; // EXTR X0, X0, X0, #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -508,10 +505,10 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntLsb)] uint lsb) + 0x80000000u, 0xFFFFFFFFu)] uint wm, + [Values(0u, 15u, 16u, 31u)] uint lsb) { uint opcode = 0x13800000; // EXTR W0, W0, W0, #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -529,9 +526,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm) { uint opcode = 0x9AC02000; // LSLV X0, X0, X0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -548,9 +545,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm) + 0x80000000u, 0xFFFFFFFFu)] uint wm) { uint opcode = 0x1AC02000; // LSLV W0, W0, W0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -567,9 +564,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm) { uint opcode = 0x9AC02400; // LSRV X0, X0, X0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -586,9 +583,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm) + 0x80000000u, 0xFFFFFFFFu)] uint wm) { uint opcode = 0x1AC02400; // LSRV W0, W0, W0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -605,11 +602,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0xAA200000; // ORN X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -627,11 +624,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x2A200000; // ORN W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -649,11 +646,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0xAA000000; // ORR X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -671,11 +668,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // <LSL, LSR, ASR, ROR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x2A000000; // ORR W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -693,9 +690,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm) { uint opcode = 0x9AC02C00; // RORV X0, X0, X0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -712,9 +709,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm) + 0x80000000u, 0xFFFFFFFFu)] uint wm) { uint opcode = 0x1AC02C00; // RORV W0, W0, W0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -731,9 +728,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values] bool carryIn) { uint opcode = 0xDA000000; // SBC X0, X0, X0 @@ -751,9 +748,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values] bool carryIn) { uint opcode = 0x5A000000; // SBC W0, W0, W0 @@ -771,9 +768,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values] bool carryIn) { uint opcode = 0xFA000000; // SBCS X0, X0, X0 @@ -791,9 +788,9 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values] bool carryIn) { uint opcode = 0x7A000000; // SBCS W0, W0, W0 @@ -811,11 +808,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0xCB000000; // SUB X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -833,11 +830,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x4B000000; // SUB W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -855,11 +852,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR> - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) + [Values(0u, 31u, 32u, 63u)] uint amount) { uint opcode = 0xEB000000; // SUBS X0, X0, X0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -877,11 +874,11 @@ namespace Ryujinx.Tests.Cpu [Values(1u, 31u)] uint rn, [Values(2u, 31u)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn, + 0x80000000u, 0xFFFFFFFFu)] uint wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm, + 0x80000000u, 0xFFFFFFFFu)] uint wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // <LSL, LSR, ASR> - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) + [Values(0u, 15u, 16u, 31u)] uint amount) { uint opcode = 0x6B000000; // SUBS W0, W0, W0, LSL #0 opcode |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); @@ -895,4 +892,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -} +}
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