diff options
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestAlu32.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestAlu32.cs | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs index c7537cd9..0d009e90 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs @@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu #region "ValueSource (Opcodes)" private static uint[] _SU_H_AddSub_8_() { - return new uint[] + return new[] { 0xe6100f90u, // SADD8 R0, R0, R0 0xe6100ff0u, // SSUB8 R0, R0, R0 @@ -27,7 +27,7 @@ namespace Ryujinx.Tests.Cpu private static uint[] _Ssat_Usat_() { - return new uint[] + return new[] { 0xe6a00010u, // SSAT R0, #1, R0, LSL #0 0xe6a00050u, // SSAT R0, #1, R0, ASR #32 @@ -38,7 +38,7 @@ namespace Ryujinx.Tests.Cpu private static uint[] _Ssat16_Usat16_() { - return new uint[] + return new[] { 0xe6a00f30u, // SSAT16 R0, #1, R0 0xe6e00f30u, // USAT16 R0, #0, R0 @@ -47,7 +47,7 @@ namespace Ryujinx.Tests.Cpu private static uint[] _Lsr_Lsl_Asr_Ror_() { - return new uint[] + return new[] { 0xe1b00030u, // LSRS R0, R0, R0 0xe1b00010u, // LSLS R0, R0, R0 @@ -63,7 +63,7 @@ namespace Ryujinx.Tests.Cpu public void Rbit_32bit([Values(0u, 0xdu)] uint rd, [Values(1u, 0xdu)] uint rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn) + 0x80000000u, 0xFFFFFFFFu)] uint wn) { uint opcode = 0xe6ff0f30u; // RBIT R0, R0 opcode |= ((rm & 15) << 0) | ((rd & 15) << 12); @@ -76,10 +76,10 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise] - public void Lsr_Lsl_Asr_Ror([ValueSource("_Lsr_Lsl_Asr_Ror_")] uint opcode, + public void Lsr_Lsl_Asr_Ror([ValueSource(nameof(_Lsr_Lsl_Asr_Ror_))] uint opcode, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint shiftValue, - [Range(0, 31)] [Values(32, 256, 768, -1, -23)] int shiftAmount) + 0x80000000u, 0xFFFFFFFFu)] uint shiftValue, + [Range(0, 31)] int shiftAmount) { uint rd = 0; uint rm = 1; @@ -130,13 +130,13 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise] - public void Ssat_Usat([ValueSource("_Ssat_Usat_")] uint opcode, + public void Ssat_Usat([ValueSource(nameof(_Ssat_Usat_))] uint opcode, [Values(0u, 0xdu)] uint rd, [Values(1u, 0xdu)] uint rn, [Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint sat, [Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint shift, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn) + 0x80000000u, 0xFFFFFFFFu)] uint wn) { opcode |= ((rn & 15) << 0) | ((shift & 31) << 7) | ((rd & 15) << 12) | ((sat & 31) << 16); @@ -148,12 +148,12 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise] - public void Ssat16_Usat16([ValueSource("_Ssat16_Usat16_")] uint opcode, + public void Ssat16_Usat16([ValueSource(nameof(_Ssat16_Usat16_))] uint opcode, [Values(0u, 0xdu)] uint rd, [Values(1u, 0xdu)] uint rn, [Values(0u, 7u, 8u, 0xfu)] uint sat, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn) + 0x80000000u, 0xFFFFFFFFu)] uint wn) { opcode |= ((rn & 15) << 0) | ((rd & 15) << 12) | ((sat & 15) << 16); @@ -165,7 +165,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise] - public void SU_H_AddSub_8([ValueSource("_SU_H_AddSub_8_")] uint opcode, + public void SU_H_AddSub_8([ValueSource(nameof(_SU_H_AddSub_8_))] uint opcode, [Values(0u, 0xdu)] uint rd, [Values(1u)] uint rm, [Values(2u)] uint rn, @@ -206,4 +206,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -} +}
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