diff options
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestAlu.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestAlu.cs | 27 |
1 files changed, 12 insertions, 15 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs index 0c4aa3b0..7318d979 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs @@ -1,7 +1,6 @@ #define Alu using NUnit.Framework; - using System.Collections.Generic; namespace Ryujinx.Tests.Cpu @@ -91,12 +90,10 @@ namespace Ryujinx.Tests.Cpu } #endregion - private const int RndCnt = 2; - [Test, Pairwise, Description("CLS <Xd>, <Xn>")] public void Cls_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, - [ValueSource("_GenLeadingSignsX_")] [Random(RndCnt)] ulong xn) + [ValueSource(nameof(_GenLeadingSignsX_))] ulong xn) { uint opcode = 0xDAC01400; // CLS X0, X0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -111,7 +108,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("CLS <Wd>, <Wn>")] public void Cls_32bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, - [ValueSource("_GenLeadingSignsW_")] [Random(RndCnt)] uint wn) + [ValueSource(nameof(_GenLeadingSignsW_))] uint wn) { uint opcode = 0x5AC01400; // CLS W0, W0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -126,7 +123,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("CLZ <Xd>, <Xn>")] public void Clz_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, - [ValueSource("_GenLeadingZerosX_")] [Random(RndCnt)] ulong xn) + [ValueSource(nameof(_GenLeadingZerosX_))] ulong xn) { uint opcode = 0xDAC01000; // CLZ X0, X0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -141,7 +138,7 @@ namespace Ryujinx.Tests.Cpu [Test, Pairwise, Description("CLZ <Wd>, <Wn>")] public void Clz_32bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, - [ValueSource("_GenLeadingZerosW_")] [Random(RndCnt)] uint wn) + [ValueSource(nameof(_GenLeadingZerosW_))] uint wn) { uint opcode = 0x5AC01000; // CLZ W0, W0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -157,7 +154,7 @@ namespace Ryujinx.Tests.Cpu public void Rbit_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn) { uint opcode = 0xDAC00000; // RBIT X0, X0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -173,7 +170,7 @@ namespace Ryujinx.Tests.Cpu public void Rbit_32bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn) + 0x80000000u, 0xFFFFFFFFu)] uint wn) { uint opcode = 0x5AC00000; // RBIT W0, W0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -189,7 +186,7 @@ namespace Ryujinx.Tests.Cpu public void Rev16_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn) { uint opcode = 0xDAC00400; // REV16 X0, X0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -205,7 +202,7 @@ namespace Ryujinx.Tests.Cpu public void Rev16_32bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn) + 0x80000000u, 0xFFFFFFFFu)] uint wn) { uint opcode = 0x5AC00400; // REV16 W0, W0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -221,7 +218,7 @@ namespace Ryujinx.Tests.Cpu public void Rev32_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn) { uint opcode = 0xDAC00800; // REV32 X0, X0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -237,7 +234,7 @@ namespace Ryujinx.Tests.Cpu public void Rev32_32bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn) + 0x80000000u, 0xFFFFFFFFu)] uint wn) { uint opcode = 0x5AC00800; // REV W0, W0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -253,7 +250,7 @@ namespace Ryujinx.Tests.Cpu public void Rev64_64bit([Values(0u, 31u)] uint rd, [Values(1u, 31u)] uint rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn) { uint opcode = 0xDAC00C00; // REV64 X0, X0 opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -266,4 +263,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -} +}
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