diff options
| author | TSRBerry <20988865+TSRBerry@users.noreply.github.com> | 2023-07-01 04:14:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-01 02:14:34 +0000 |
| commit | e9848339ddac3d6fe32a0ce0fbe6029c4ad40429 (patch) | |
| tree | 8674ac269970ae79efca9a080ec626a62918505e /src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs | |
| parent | 6e28a4dd13df0ab866e6a178086abe36ca4a2b25 (diff) | |
[Ryujinx.Tests] Address dotnet-format issues (#5389)1.1.943
* dotnet format style --severity info
Some changes were manually reverted.
* dotnet format analyzers --serverity info
Some changes have been minimally adapted.
* Restore a few unused methods and variables
* Fix new dotnet-format issues after rebase
* Address review comments
* Address most dotnet format whitespace warnings
* Apply dotnet format whitespace formatting
A few of them have been manually reverted and the corresponding warning was silenced
* Format if-blocks correctly
* Run dotnet format after rebase and remove unused usings
- analyzers
- style
- whitespace
* Add comments to disabled warnings
* Simplify properties and array initialization, Use const when possible, Remove trailing commas
* cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress
* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"
This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.
* dotnet format whitespace after rebase
* Apply suggestions from code review
Co-authored-by: Ac_K <Acoustik666@gmail.com>
* First dotnet format pass
* Fix naming rule violations
* Remove naming rule violation exceptions
* Fix comment style
* Use targeted new
* Remove redundant code
* Remove comment alignment
* Remove naming rule exceptions
* Add trailing commas
* Use nameof expression
* Reformat to add remaining trailing commas
---------
Co-authored-by: Ac_K <Acoustik666@gmail.com>
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs | 51 |
1 files changed, 32 insertions, 19 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs index e7fad89f..f81d22c2 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs @@ -10,30 +10,41 @@ namespace Ryujinx.Tests.Cpu { #if SimdShImm32 -#region "ValueSource (Types)" + #region "ValueSource (Types)" private static ulong[] _1D_() { - return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _2S_() { - return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] + { + 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _4H_() { - return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] + { + 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _8B_() { - return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] + { + 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul, + }; } -#endregion + #endregion -#region "ValueSource (Opcodes)" + #region "ValueSource (Opcodes)" private static uint[] _Vshr_Imm_SU8_() { return new[] @@ -41,7 +52,7 @@ namespace Ryujinx.Tests.Cpu 0xf2880010u, // VSHR.S8 D0, D0, #8 0xf2880110u, // VSRA.S8 D0, D0, #8 0xf2880210u, // VRSHR.S8 D0, D0, #8 - 0xf2880310u // VRSRA.S8 D0, D0, #8 + 0xf2880310u, // VRSRA.S8 D0, D0, #8 }; } @@ -52,7 +63,7 @@ namespace Ryujinx.Tests.Cpu 0xf2900010u, // VSHR.S16 D0, D0, #16 0xf2900110u, // VSRA.S16 D0, D0, #16 0xf2900210u, // VRSHR.S16 D0, D0, #16 - 0xf2900310u // VRSRA.S16 D0, D0, #16 + 0xf2900310u, // VRSRA.S16 D0, D0, #16 }; } @@ -63,7 +74,7 @@ namespace Ryujinx.Tests.Cpu 0xf2a00010u, // VSHR.S32 D0, D0, #32 0xf2a00110u, // VSRA.S32 D0, D0, #32 0xf2a00210u, // VRSHR.S32 D0, D0, #32 - 0xf2a00310u // VRSRA.S32 D0, D0, #32 + 0xf2a00310u, // VRSRA.S32 D0, D0, #32 }; } @@ -73,7 +84,7 @@ namespace Ryujinx.Tests.Cpu { 0xf2800190u, // VSRA.S64 D0, D0, #64 0xf2800290u, // VRSHR.S64 D0, D0, #64 - 0xf2800090u // VSHR.S64 D0, D0, #64 + 0xf2800090u, // VSHR.S64 D0, D0, #64 }; } @@ -83,7 +94,7 @@ namespace Ryujinx.Tests.Cpu { 0xf2800910u, // VORR.I16 D0, #0 (immediate value changes it into QSHRN) 0xf2800950u, // VORR.I16 Q0, #0 (immediate value changes it into QRSHRN) - 0xf2800850u // VMOV.I16 Q0, #0 (immediate value changes it into RSHRN) + 0xf2800850u, // VMOV.I16 Q0, #0 (immediate value changes it into RSHRN) }; } @@ -92,10 +103,10 @@ namespace Ryujinx.Tests.Cpu return new[] { 0xf3800810u, // VMOV.I16 D0, #0x80 (immediate value changes it into QSHRUN) - 0xf3800850u // VMOV.I16 Q0, #0x80 (immediate value changes it into QRSHRUN) + 0xf3800850u, // VMOV.I16 Q0, #0x80 (immediate value changes it into QRSHRUN) }; } -#endregion + #endregion private const int RndCnt = 2; private const int RndCntShiftImm = 2; @@ -171,12 +182,14 @@ namespace Ryujinx.Tests.Cpu { opcode |= 1 << 6; - rd >>= 1; rd <<= 1; - rm >>= 1; rm <<= 1; + rd >>= 1; + rd <<= 1; + rm >>= 1; + rm <<= 1; } opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= (imm6 & 0x3f) << 16; @@ -312,4 +325,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -}
\ No newline at end of file +} |