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| author | TSRBerry <20988865+TSRBerry@users.noreply.github.com> | 2023-07-01 04:14:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-01 02:14:34 +0000 |
| commit | e9848339ddac3d6fe32a0ce0fbe6029c4ad40429 (patch) | |
| tree | 8674ac269970ae79efca9a080ec626a62918505e /src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs | |
| parent | 6e28a4dd13df0ab866e6a178086abe36ca4a2b25 (diff) | |
[Ryujinx.Tests] Address dotnet-format issues (#5389)1.1.943
* dotnet format style --severity info
Some changes were manually reverted.
* dotnet format analyzers --serverity info
Some changes have been minimally adapted.
* Restore a few unused methods and variables
* Fix new dotnet-format issues after rebase
* Address review comments
* Address most dotnet format whitespace warnings
* Apply dotnet format whitespace formatting
A few of them have been manually reverted and the corresponding warning was silenced
* Format if-blocks correctly
* Run dotnet format after rebase and remove unused usings
- analyzers
- style
- whitespace
* Add comments to disabled warnings
* Simplify properties and array initialization, Use const when possible, Remove trailing commas
* cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress
* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"
This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.
* dotnet format whitespace after rebase
* Apply suggestions from code review
Co-authored-by: Ac_K <Acoustik666@gmail.com>
* First dotnet format pass
* Fix naming rule violations
* Remove naming rule violation exceptions
* Fix comment style
* Use targeted new
* Remove redundant code
* Remove comment alignment
* Remove naming rule exceptions
* Add trailing commas
* Use nameof expression
* Reformat to add remaining trailing commas
---------
Co-authored-by: Ac_K <Acoustik666@gmail.com>
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs | 84 |
1 files changed, 48 insertions, 36 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs index 31b23604..1b670da7 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs @@ -11,7 +11,7 @@ namespace Ryujinx.Tests.Cpu { #if SimdRegElemF -#region "ValueSource (Types)" + #region "ValueSource (Types)" private static IEnumerable<ulong> _1S_F_() { yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue) @@ -23,19 +23,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x00000000007FFFFFul; // +Max Subnormal yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x0000000080000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0x00000000FF800000ul; // -Infinity yield return 0x000000007F800000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN) yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload) @@ -65,19 +65,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x007FFFFF007FFFFFul; // +Max Subnormal yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x8000000080000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0xFF800000FF800000ul; // -Infinity yield return 0x7F8000007F800000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN) yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload) @@ -106,19 +106,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x8000000000000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0xFFF0000000000000ul; // -Infinity yield return 0x7FF0000000000000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN) yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload) @@ -135,15 +135,15 @@ namespace Ryujinx.Tests.Cpu yield return rnd2; } } -#endregion + #endregion -#region "ValueSource (Opcodes)" + #region "ValueSource (Opcodes)" private static uint[] _F_Mla_Mls_Se_S_() { return new[] { 0x5F821020u, // FMLA S0, S1, V2.S[0] - 0x5F825020u // FMLS S0, S1, V2.S[0] + 0x5F825020u, // FMLS S0, S1, V2.S[0] }; } @@ -152,7 +152,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x5FC21020u, // FMLA D0, D1, V2.D[0] - 0x5FC25020u // FMLS D0, D1, V2.D[0] + 0x5FC25020u, // FMLS D0, D1, V2.D[0] }; } @@ -161,7 +161,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x0F801000u, // FMLA V0.2S, V0.2S, V0.S[0] - 0x0F805000u // FMLS V0.2S, V0.2S, V0.S[0] + 0x0F805000u, // FMLS V0.2S, V0.2S, V0.S[0] }; } @@ -170,7 +170,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x4FC01000u, // FMLA V0.2D, V0.2D, V0.D[0] - 0x4FC05000u // FMLS V0.2D, V0.2D, V0.D[0] + 0x4FC05000u, // FMLS V0.2D, V0.2D, V0.D[0] }; } @@ -179,7 +179,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x5F829020u, // FMUL S0, S1, V2.S[0] - 0x7F829020u // FMULX S0, S1, V2.S[0] + 0x7F829020u, // FMULX S0, S1, V2.S[0] }; } @@ -188,7 +188,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x5FC29020u, // FMUL D0, D1, V2.D[0] - 0x7FC29020u // FMULX D0, D1, V2.D[0] + 0x7FC29020u, // FMULX D0, D1, V2.D[0] }; } @@ -197,7 +197,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x0F809000u, // FMUL V0.2S, V0.2S, V0.S[0] - 0x2F809000u // FMULX V0.2S, V0.2S, V0.S[0] + 0x2F809000u, // FMULX V0.2S, V0.2S, V0.S[0] }; } @@ -206,18 +206,20 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x4FC09000u, // FMUL V0.2D, V0.2D, V0.D[0] - 0x6FC09000u // FMULX V0.2D, V0.2D, V0.D[0] + 0x6FC09000u, // FMULX V0.2D, V0.2D, V0.D[0] }; } -#endregion + #endregion private const int RndCnt = 2; - private static readonly bool NoZeros = false; - private static readonly bool NoInfs = false; - private static readonly bool NoNaNs = false; + private static readonly bool _noZeros = false; + private static readonly bool _noInfs = false; + private static readonly bool _noNaNs = false; - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Mla_Mls_Se_S([ValueSource(nameof(_F_Mla_Mls_Se_S_))] uint opcodes, [ValueSource(nameof(_1S_F_))] ulong z, [ValueSource(nameof(_1S_F_))] ulong a, @@ -243,7 +245,9 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsS); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Mla_Mls_Se_D([ValueSource(nameof(_F_Mla_Mls_Se_D_))] uint opcodes, [ValueSource(nameof(_1D_F_))] ulong z, [ValueSource(nameof(_1D_F_))] ulong a, @@ -268,9 +272,11 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsD); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Mla_Mls_Ve_2S_4S([ValueSource(nameof(_F_Mla_Mls_Ve_2S_4S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_2S_F_))] ulong z, @@ -300,9 +306,11 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsS); } - [Test, Pairwise] [Explicit] // Fused. + // Fused. + [Test, Pairwise] + [Explicit] public void F_Mla_Mls_Ve_2D([ValueSource(nameof(_F_Mla_Mls_Ve_2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_F_))] ulong z, @@ -329,7 +337,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(Fpsr.Ioc | Fpsr.Idc, FpSkips.IfUnderflow, FpTolerances.UpToOneUlpsD); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Mul_Mulx_Se_S([ValueSource(nameof(_F_Mul_Mulx_Se_S_))] uint opcodes, [ValueSource(nameof(_1S_F_))] ulong a, [ValueSource(nameof(_2S_F_))] ulong b, @@ -355,7 +364,8 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Mul_Mulx_Se_D([ValueSource(nameof(_F_Mul_Mulx_Se_D_))] uint opcodes, [ValueSource(nameof(_1D_F_))] ulong a, [ValueSource(nameof(_1D_F_))] ulong b, @@ -380,9 +390,10 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Mul_Mulx_Ve_2S_4S([ValueSource(nameof(_F_Mul_Mulx_Ve_2S_4S_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_2S_F_))] ulong z, @@ -412,9 +423,10 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Idc); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Mul_Mulx_Ve_2D([ValueSource(nameof(_F_Mul_Mulx_Ve_2D_))] uint opcodes, - [Values(0u)] uint rd, + [Values(0u)] uint rd, [Values(1u, 0u)] uint rn, [Values(2u, 0u)] uint rm, [ValueSource(nameof(_1D_F_))] ulong z, |