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authorMary <mary@mary.zone>2023-06-14 18:02:41 +0200
committerGitHub <noreply@github.com>2023-06-14 18:02:41 +0200
commit6f28c4abadfead6fb5146caa5775dba1641bd79f (patch)
tree921d19035ddf57f31aa9cfa78a81699848169a36 /src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs
parent105c9712c1cf8400b3ff34c3a69a8af81ee4431e (diff)
test: Make tests runnable on system without 4KiB page size (#5184)1.1.892
* ARMeilleure: Do not hardcode 4KiB page size in JitCache * test: Do not hardcode page size to 4KiB for Ryujinx.Tests.Memory.Tests Fix running tests on Asahi Linux with 16KiB pages. * test: Do not hardcode page size to 4KiB for Ryujinx.Tests.Cpu Fix running tests on Asahi Linux. Test runner still crash when trying to run all test suite. * test: Do not hardcode page size to 4KiB for Ryujinx.Tests.Cpu Fix somecrashes on Asahi Linux. * test: Ignore Vshl test on ARM64 due to unicorn crashes * test: Workaround hardcoded size on some tests Change mapping of code and data in case of non 4KiB configuration. * test: Make CpuTestT32Flow depends on code address Fix failure with different page size. * test: Disable CpuTestThumb.TestRandomTestCases when page size isn't 4KiB The test data needs to be reevaluated to take different page size into account. * Address gdkchan's comments
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs')
-rw-r--r--src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs34
1 files changed, 18 insertions, 16 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs
index 2f9504cb..c88c02c1 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs
@@ -1,6 +1,7 @@
#define SimdMemory32
using ARMeilleure.State;
+using Ryujinx.Memory;
using NUnit.Framework;
using System;
@@ -9,6 +10,7 @@ namespace Ryujinx.Tests.Cpu
[Category("SimdMemory32")]
public sealed class CpuTestSimdMemory32 : CpuTest32
{
+ private static readonly uint TestOffset = DataBaseAddress + 0x500;
#if SimdMemory32
private uint[] _ldStModes =
@@ -42,7 +44,7 @@ namespace Ryujinx.Tests.Cpu
[Range(0u, 3u)] uint n,
[Values(0x0u)] uint offset)
{
- var data = GenerateVectorSequence(0x1000);
+ var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
SetWorkingMemory(0, data);
uint opcode = 0xf4a00000u; // VLD1.8 {D0[0]}, [R0], R0
@@ -58,7 +60,7 @@ namespace Ryujinx.Tests.Cpu
opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
- SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
+ SingleOpcode(opcode, r0: TestOffset, r1: offset, sp: TestOffset);
CompareAgainstUnicorn();
}
@@ -72,7 +74,7 @@ namespace Ryujinx.Tests.Cpu
[Values] bool t,
[Values(0x0u)] uint offset)
{
- var data = GenerateVectorSequence(0x1000);
+ var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
SetWorkingMemory(0, data);
uint opcode = 0xf4a00c00u; // VLD1.8 {D0[0]}, [R0], R0
@@ -85,7 +87,7 @@ namespace Ryujinx.Tests.Cpu
opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc.
if (t) opcode |= 1 << 5;
- SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
+ SingleOpcode(opcode, r0: TestOffset, r1: offset, sp: TestOffset);
CompareAgainstUnicorn();
}
@@ -98,7 +100,7 @@ namespace Ryujinx.Tests.Cpu
[Range(0u, 10u)] uint mode,
[Values(0x0u)] uint offset)
{
- var data = GenerateVectorSequence(0x1000);
+ var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
SetWorkingMemory(0, data);
uint opcode = 0xf4200000u; // VLD4.8 {D0, D1, D2, D3}, [R0], R0
@@ -114,7 +116,7 @@ namespace Ryujinx.Tests.Cpu
opcode |= ((vd & 0x10) << 18);
opcode |= ((vd & 0xf) << 12);
- SingleOpcode(opcode, r0: 0x2500, r1: offset, sp: 0x2500);
+ SingleOpcode(opcode, r0: TestOffset, r1: offset, sp: TestOffset);
CompareAgainstUnicorn();
}
@@ -128,7 +130,7 @@ namespace Ryujinx.Tests.Cpu
[Range(0u, 3u)] uint n,
[Values(0x0u)] uint offset)
{
- var data = GenerateVectorSequence(0x1000);
+ var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
SetWorkingMemory(0, data);
(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
@@ -146,7 +148,7 @@ namespace Ryujinx.Tests.Cpu
opcode |= (n & 3) << 8; // ST1 is 0, ST2 is 1 etc.
- SingleOpcode(opcode, r0: 0x2500, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: 0x2500);
+ SingleOpcode(opcode, r0: TestOffset, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: TestOffset);
CompareAgainstUnicorn();
}
@@ -159,7 +161,7 @@ namespace Ryujinx.Tests.Cpu
[Range(0u, 10u)] uint mode,
[Values(0x0u)] uint offset)
{
- var data = GenerateVectorSequence(0x1000);
+ var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
SetWorkingMemory(0, data);
(V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
@@ -177,7 +179,7 @@ namespace Ryujinx.Tests.Cpu
opcode |= ((vd & 0x10) << 18);
opcode |= ((vd & 0xf) << 12);
- SingleOpcode(opcode, r0: 0x2500, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: 0x2500);
+ SingleOpcode(opcode, r0: TestOffset, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: TestOffset);
CompareAgainstUnicorn();
}
@@ -189,7 +191,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0x1u, 0x32u)] uint regs,
[Values] bool single)
{
- var data = GenerateVectorSequence(0x1000);
+ var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
SetWorkingMemory(0, data);
uint opcode = 0xec100a00u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
@@ -225,7 +227,7 @@ namespace Ryujinx.Tests.Cpu
opcode |= regs & 0xff;
- SingleOpcode(opcode, r0: 0x2500, sp: 0x2500);
+ SingleOpcode(opcode, r0: TestOffset, sp: TestOffset);
CompareAgainstUnicorn();
}
@@ -237,7 +239,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0x0u)] uint imm,
[Values] bool sub)
{
- var data = GenerateVectorSequence(0x1000);
+ var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
SetWorkingMemory(0, data);
uint opcode = 0xed900a00u; // VLDR.32 S0, [R0, #0]
@@ -260,7 +262,7 @@ namespace Ryujinx.Tests.Cpu
}
opcode |= imm & 0xff;
- SingleOpcode(opcode, r0: 0x2500);
+ SingleOpcode(opcode, r0: TestOffset);
CompareAgainstUnicorn();
}
@@ -272,7 +274,7 @@ namespace Ryujinx.Tests.Cpu
[Values(0x0u)] uint imm,
[Values] bool sub)
{
- var data = GenerateVectorSequence(0x1000);
+ var data = GenerateVectorSequence((int)MemoryBlock.GetPageSize());
SetWorkingMemory(0, data);
uint opcode = 0xed800a00u; // VSTR.32 S0, [R0, #0]
@@ -297,7 +299,7 @@ namespace Ryujinx.Tests.Cpu
(V128 vec1, V128 vec2, _, _) = GenerateTestVectors();
- SingleOpcode(opcode, r0: 0x2500, v0: vec1, v1: vec2);
+ SingleOpcode(opcode, r0: TestOffset, v0: vec1, v1: vec2);
CompareAgainstUnicorn();
}
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-03-20 19:17:21 +0000