diff options
| author | TSRBerry <20988865+TSRBerry@users.noreply.github.com> | 2023-07-01 04:14:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-01 02:14:34 +0000 |
| commit | e9848339ddac3d6fe32a0ce0fbe6029c4ad40429 (patch) | |
| tree | 8674ac269970ae79efca9a080ec626a62918505e /src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs | |
| parent | 6e28a4dd13df0ab866e6a178086abe36ca4a2b25 (diff) | |
[Ryujinx.Tests] Address dotnet-format issues (#5389)1.1.943
* dotnet format style --severity info
Some changes were manually reverted.
* dotnet format analyzers --serverity info
Some changes have been minimally adapted.
* Restore a few unused methods and variables
* Fix new dotnet-format issues after rebase
* Address review comments
* Address most dotnet format whitespace warnings
* Apply dotnet format whitespace formatting
A few of them have been manually reverted and the corresponding warning was silenced
* Format if-blocks correctly
* Run dotnet format after rebase and remove unused usings
- analyzers
- style
- whitespace
* Add comments to disabled warnings
* Simplify properties and array initialization, Use const when possible, Remove trailing commas
* cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress
* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"
This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.
* dotnet format whitespace after rebase
* Apply suggestions from code review
Co-authored-by: Ac_K <Acoustik666@gmail.com>
* First dotnet format pass
* Fix naming rule violations
* Remove naming rule violation exceptions
* Fix comment style
* Use targeted new
* Remove redundant code
* Remove comment alignment
* Remove naming rule exceptions
* Add trailing commas
* Use nameof expression
* Reformat to add remaining trailing commas
---------
Co-authored-by: Ac_K <Acoustik666@gmail.com>
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs | 49 |
1 files changed, 28 insertions, 21 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs index 50915fd3..28f00d58 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs @@ -10,10 +10,10 @@ namespace Ryujinx.Tests.Cpu [Category("SimdMemory32")] public sealed class CpuTestSimdMemory32 : CpuTest32 { - private static readonly uint TestOffset = DataBaseAddress + 0x500; + private static readonly uint _testOffset = DataBaseAddress + 0x500; #if SimdMemory32 - private uint[] _ldStModes = + private readonly uint[] _ldStModes = { // LD1 0b0111, @@ -32,7 +32,7 @@ namespace Ryujinx.Tests.Cpu // LD4 0b0000, - 0b0001 + 0b0001, }; [Test, Pairwise, Description("VLDn.<size> <list>, [<Rn> {:<align>}]{ /!/, <Rm>} (single n element structure)")] @@ -51,16 +51,16 @@ namespace Ryujinx.Tests.Cpu opcode |= ((size & 3) << 10) | ((rn & 15) << 16) | (rm & 15); - uint index_align = (index << (int)(1 + size)) & 15; + uint indexAlign = (index << (int)(1 + size)) & 15; - opcode |= (index_align) << 4; + opcode |= (indexAlign) << 4; opcode |= ((vd & 0x10) << 18); opcode |= ((vd & 0xf) << 12); opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc. - SingleOpcode(opcode, r0: TestOffset, r1: offset, sp: TestOffset); + SingleOpcode(opcode, r0: _testOffset, r1: offset, sp: _testOffset); CompareAgainstUnicorn(); } @@ -85,9 +85,12 @@ namespace Ryujinx.Tests.Cpu opcode |= ((vd & 0xf) << 12); opcode |= (n & 3) << 8; // LD1 is 0, LD2 is 1 etc. - if (t) opcode |= 1 << 5; + if (t) + { + opcode |= 1 << 5; + } - SingleOpcode(opcode, r0: TestOffset, r1: offset, sp: TestOffset); + SingleOpcode(opcode, r0: _testOffset, r1: offset, sp: _testOffset); CompareAgainstUnicorn(); } @@ -116,7 +119,7 @@ namespace Ryujinx.Tests.Cpu opcode |= ((vd & 0x10) << 18); opcode |= ((vd & 0xf) << 12); - SingleOpcode(opcode, r0: TestOffset, r1: offset, sp: TestOffset); + SingleOpcode(opcode, r0: _testOffset, r1: offset, sp: _testOffset); CompareAgainstUnicorn(); } @@ -139,16 +142,16 @@ namespace Ryujinx.Tests.Cpu opcode |= ((size & 3) << 10) | ((rn & 15) << 16) | (rm & 15); - uint index_align = (index << (int)(1 + size)) & 15; + uint indexAlign = (index << (int)(1 + size)) & 15; - opcode |= (index_align) << 4; + opcode |= (indexAlign) << 4; opcode |= ((vd & 0x10) << 18); opcode |= ((vd & 0xf) << 12); opcode |= (n & 3) << 8; // ST1 is 0, ST2 is 1 etc. - SingleOpcode(opcode, r0: TestOffset, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: TestOffset); + SingleOpcode(opcode, r0: _testOffset, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: _testOffset); CompareAgainstUnicorn(); } @@ -179,7 +182,7 @@ namespace Ryujinx.Tests.Cpu opcode |= ((vd & 0x10) << 18); opcode |= ((vd & 0xf) << 12); - SingleOpcode(opcode, r0: TestOffset, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: TestOffset); + SingleOpcode(opcode, r0: _testOffset, r1: offset, v1: vec1, v2: vec2, v3: vec3, v4: vec4, sp: _testOffset); CompareAgainstUnicorn(); } @@ -201,7 +204,7 @@ namespace Ryujinx.Tests.Cpu // Note: 3rd 0 leaves a space for "D". 0b0100, // Increment after. 0b0101, // Increment after. (!) - 0b1001 // Decrement before. (!) + 0b1001, // Decrement before. (!) }; opcode |= ((vldmModes[mode] & 15) << 21); @@ -212,7 +215,11 @@ namespace Ryujinx.Tests.Cpu opcode |= ((uint)(single ? 0 : 1) << 8); - if (!single) regs = (regs << 1); // Low bit must be 0 - must be even number of registers. + if (!single) + { + regs <<= 1; // Low bit must be 0 - must be even number of registers. + } + uint regSize = single ? 1u : 2u; if (vd + (regs / regSize) > 32) // Can't address further than S31 or D31. @@ -227,7 +234,7 @@ namespace Ryujinx.Tests.Cpu opcode |= regs & 0xff; - SingleOpcode(opcode, r0: TestOffset, sp: TestOffset); + SingleOpcode(opcode, r0: _testOffset, sp: _testOffset); CompareAgainstUnicorn(); } @@ -262,7 +269,7 @@ namespace Ryujinx.Tests.Cpu } opcode |= imm & 0xff; - SingleOpcode(opcode, r0: TestOffset); + SingleOpcode(opcode, r0: _testOffset); CompareAgainstUnicorn(); } @@ -299,12 +306,12 @@ namespace Ryujinx.Tests.Cpu (V128 vec1, V128 vec2, _, _) = GenerateTestVectors(); - SingleOpcode(opcode, r0: TestOffset, v0: vec1, v1: vec2); + SingleOpcode(opcode, r0: _testOffset, v0: vec1, v1: vec2); CompareAgainstUnicorn(); } - private (V128, V128, V128, V128) GenerateTestVectors() + private static (V128, V128, V128, V128) GenerateTestVectors() { return ( new V128(-12.43f, 1872.23f, 4456.23f, -5622.2f), @@ -314,7 +321,7 @@ namespace Ryujinx.Tests.Cpu ); } - private byte[] GenerateVectorSequence(int length) + private static byte[] GenerateVectorSequence(int length) { int floatLength = length >> 2; float[] data = new float[floatLength]; @@ -330,4 +337,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -}
\ No newline at end of file +} |