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authorTSRBerry <20988865+TSRBerry@users.noreply.github.com>2023-07-01 04:14:34 +0200
committerGitHub <noreply@github.com>2023-07-01 02:14:34 +0000
commite9848339ddac3d6fe32a0ce0fbe6029c4ad40429 (patch)
tree8674ac269970ae79efca9a080ec626a62918505e /src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
parent6e28a4dd13df0ab866e6a178086abe36ca4a2b25 (diff)
[Ryujinx.Tests] Address dotnet-format issues (#5389)1.1.943
* dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Fix new dotnet-format issues after rebase * Address review comments * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Format if-blocks correctly * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Add comments to disabled warnings * Simplify properties and array initialization, Use const when possible, Remove trailing commas * cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * Apply suggestions from code review Co-authored-by: Ac_K <Acoustik666@gmail.com> * First dotnet format pass * Fix naming rule violations * Remove naming rule violation exceptions * Fix comment style * Use targeted new * Remove redundant code * Remove comment alignment * Remove naming rule exceptions * Add trailing commas * Use nameof expression * Reformat to add remaining trailing commas --------- Co-authored-by: Ac_K <Acoustik666@gmail.com>
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs')
-rw-r--r--src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs116
1 files changed, 66 insertions, 50 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
index d5ac3c27..83dc0770 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
@@ -10,64 +10,80 @@ namespace Ryujinx.Tests.Cpu
{
#if SimdIns
-#region "ValueSource"
+ #region "ValueSource"
private static ulong[] _1D_()
{
- return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _2S_()
{
- return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _4H_()
{
- return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _8B_()
{
- return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _8B4H_()
{
- return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static ulong[] _8B4H2S_()
{
- return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
- 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
- 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
- 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+ 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+ 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+ 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
private static uint[] _W_()
{
- return new[] { 0x00000000u, 0x0000007Fu,
- 0x00000080u, 0x000000FFu,
- 0x00007FFFu, 0x00008000u,
- 0x0000FFFFu, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu };
+ return new[] {
+ 0x00000000u, 0x0000007Fu,
+ 0x00000080u, 0x000000FFu,
+ 0x00007FFFu, 0x00008000u,
+ 0x0000FFFFu, 0x7FFFFFFFu,
+ 0x80000000u, 0xFFFFFFFFu,
+ };
}
private static ulong[] _X_()
{
- return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+ return new[] {
+ 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
}
-#endregion
+ #endregion
[Test, Pairwise, Description("DUP <Vd>.<T>, W<n>")]
- public void Dup_Gp_W([Values(0u)] uint rd,
+ public void Dup_Gp_W([Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_W_))] uint wn,
[Values(0, 1, 2)] int size, // Q0: <8B, 4H, 2S>
@@ -80,8 +96,8 @@ namespace Ryujinx.Tests.Cpu
opcode |= (imm5 << 16);
opcode |= ((q & 1) << 30);
- uint w31 = TestContext.CurrentContext.Random.NextUInt();
- ulong z = TestContext.CurrentContext.Random.NextULong();
+ uint w31 = TestContext.CurrentContext.Random.NextUInt();
+ ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcode, x1: wn, x31: w31, v0: v0);
@@ -90,7 +106,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("DUP <Vd>.<T>, X<n>")]
- public void Dup_Gp_X([Values(0u)] uint rd,
+ public void Dup_Gp_X([Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_X_))] ulong xn)
{
@@ -98,7 +114,7 @@ namespace Ryujinx.Tests.Cpu
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
ulong x31 = TestContext.CurrentContext.Random.NextULong();
- ulong z = TestContext.CurrentContext.Random.NextULong();
+ ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE0E1(z, z);
SingleOpcode(opcode, x1: xn, x31: x31, v0: v0);
@@ -187,7 +203,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.B[<index>]")]
- public void Dup_V_8B_16B([Values(0u)] uint rd,
+ public void Dup_V_8B_16B([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B_))] ulong z,
[ValueSource(nameof(_8B_))] ulong a,
@@ -212,7 +228,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.H[<index>]")]
- public void Dup_V_4H_8H([Values(0u)] uint rd,
+ public void Dup_V_4H_8H([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_4H_))] ulong z,
[ValueSource(nameof(_4H_))] ulong a,
@@ -237,7 +253,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.S[<index>]")]
- public void Dup_V_2S_4S([Values(0u)] uint rd,
+ public void Dup_V_2S_4S([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_))] ulong z,
[ValueSource(nameof(_2S_))] ulong a,
@@ -262,7 +278,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("DUP <Vd>.<T>, <Vn>.D[<index>]")]
- public void Dup_V_2D([Values(0u)] uint rd,
+ public void Dup_V_2D([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a,
@@ -287,7 +303,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("INS <Vd>.B[<index>], W<n>")]
- public void Ins_Gp_WB([Values(0u)] uint rd,
+ public void Ins_Gp_WB([Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_8B_))] ulong z,
[ValueSource(nameof(_W_))] uint wn,
@@ -310,7 +326,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("INS <Vd>.H[<index>], W<n>")]
- public void Ins_Gp_WH([Values(0u)] uint rd,
+ public void Ins_Gp_WH([Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_4H_))] ulong z,
[ValueSource(nameof(_W_))] uint wn,
@@ -333,7 +349,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("INS <Vd>.S[<index>], W<n>")]
- public void Ins_Gp_WS([Values(0u)] uint rd,
+ public void Ins_Gp_WS([Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_2S_))] ulong z,
[ValueSource(nameof(_W_))] uint wn,
@@ -356,7 +372,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("INS <Vd>.D[<index>], X<n>")]
- public void Ins_Gp_XD([Values(0u)] uint rd,
+ public void Ins_Gp_XD([Values(0u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_X_))] ulong xn,
@@ -379,7 +395,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("INS <Vd>.B[<index1>], <Vn>.B[<index2>]")]
- public void Ins_V_BB([Values(0u)] uint rd,
+ public void Ins_V_BB([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_8B_))] ulong z,
[ValueSource(nameof(_8B_))] ulong a,
@@ -405,7 +421,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("INS <Vd>.H[<index1>], <Vn>.H[<index2>]")]
- public void Ins_V_HH([Values(0u)] uint rd,
+ public void Ins_V_HH([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_4H_))] ulong z,
[ValueSource(nameof(_4H_))] ulong a,
@@ -431,7 +447,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("INS <Vd>.S[<index1>], <Vn>.S[<index2>]")]
- public void Ins_V_SS([Values(0u)] uint rd,
+ public void Ins_V_SS([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_2S_))] ulong z,
[ValueSource(nameof(_2S_))] ulong a,
@@ -457,7 +473,7 @@ namespace Ryujinx.Tests.Cpu
}
[Test, Pairwise, Description("INS <Vd>.D[<index1>], <Vn>.D[<index2>]")]
- public void Ins_V_DD([Values(0u)] uint rd,
+ public void Ins_V_DD([Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,
[ValueSource(nameof(_1D_))] ulong z,
[ValueSource(nameof(_1D_))] ulong a,
@@ -484,7 +500,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("SMOV <Wd>, <Vn>.B[<index>]")]
public void Smov_S_BW([Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_8B_))] ulong a,
[Values(0u, 15u)] uint index)
{
@@ -507,7 +523,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("SMOV <Wd>, <Vn>.H[<index>]")]
public void Smov_S_HW([Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_4H_))] ulong a,
[Values(0u, 7u)] uint index)
{
@@ -530,7 +546,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("SMOV <Xd>, <Vn>.B[<index>]")]
public void Smov_S_BX([Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_8B_))] ulong a,
[Values(0u, 15u)] uint index)
{
@@ -552,7 +568,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("SMOV <Xd>, <Vn>.H[<index>]")]
public void Smov_S_HX([Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_4H_))] ulong a,
[Values(0u, 7u)] uint index)
{
@@ -574,7 +590,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("SMOV <Xd>, <Vn>.S[<index>]")]
public void Smov_S_SX([Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_2S_))] ulong a,
[Values(0u, 1u, 2u, 3u)] uint index)
{
@@ -596,7 +612,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("UMOV <Wd>, <Vn>.B[<index>]")]
public void Umov_S_BW([Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_8B_))] ulong a,
[Values(0u, 15u)] uint index)
{
@@ -619,7 +635,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("UMOV <Wd>, <Vn>.H[<index>]")]
public void Umov_S_HW([Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_4H_))] ulong a,
[Values(0u, 7u)] uint index)
{
@@ -642,7 +658,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("UMOV <Wd>, <Vn>.S[<index>]")]
public void Umov_S_SW([Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_2S_))] ulong a,
[Values(0u, 1u, 2u, 3u)] uint index)
{
@@ -665,7 +681,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("UMOV <Xd>, <Vn>.D[<index>]")]
public void Umov_S_DX([Values(0u, 31u)] uint rd,
- [Values(1u)] uint rn,
+ [Values(1u)] uint rn,
[ValueSource(nameof(_1D_))] ulong a,
[Values(0u, 1u)] uint index)
{
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-03-21 03:39:54 +0000