diff options
| author | TSRBerry <20988865+TSRBerry@users.noreply.github.com> | 2023-07-01 04:14:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-01 02:14:34 +0000 |
| commit | e9848339ddac3d6fe32a0ce0fbe6029c4ad40429 (patch) | |
| tree | 8674ac269970ae79efca9a080ec626a62918505e /src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs | |
| parent | 6e28a4dd13df0ab866e6a178086abe36ca4a2b25 (diff) | |
[Ryujinx.Tests] Address dotnet-format issues (#5389)1.1.943
* dotnet format style --severity info
Some changes were manually reverted.
* dotnet format analyzers --serverity info
Some changes have been minimally adapted.
* Restore a few unused methods and variables
* Fix new dotnet-format issues after rebase
* Address review comments
* Address most dotnet format whitespace warnings
* Apply dotnet format whitespace formatting
A few of them have been manually reverted and the corresponding warning was silenced
* Format if-blocks correctly
* Run dotnet format after rebase and remove unused usings
- analyzers
- style
- whitespace
* Add comments to disabled warnings
* Simplify properties and array initialization, Use const when possible, Remove trailing commas
* cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress
* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"
This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.
* dotnet format whitespace after rebase
* Apply suggestions from code review
Co-authored-by: Ac_K <Acoustik666@gmail.com>
* First dotnet format pass
* Fix naming rule violations
* Remove naming rule violation exceptions
* Fix comment style
* Use targeted new
* Remove redundant code
* Remove comment alignment
* Remove naming rule exceptions
* Add trailing commas
* Use nameof expression
* Reformat to add remaining trailing commas
---------
Co-authored-by: Ac_K <Acoustik666@gmail.com>
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs | 81 |
1 files changed, 44 insertions, 37 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs index d946b433..27e3b41a 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs @@ -11,7 +11,7 @@ namespace Ryujinx.Tests.Cpu { #if SimdImm -#region "Helper methods" + #region "Helper methods" // abcdefgh -> aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh private static ulong ExpandImm8(byte imm8) { @@ -43,19 +43,23 @@ namespace Ryujinx.Tests.Cpu return imm8; } -#endregion + #endregion -#region "ValueSource (Types)" + #region "ValueSource (Types)" private static ulong[] _2S_() { - return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static ulong[] _4H_() { - return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static IEnumerable<byte> _8BIT_IMM_() @@ -87,15 +91,15 @@ namespace Ryujinx.Tests.Cpu yield return ExpandImm8(imm8); } } -#endregion + #endregion -#region "ValueSource (Opcodes)" + #region "ValueSource (Opcodes)" private static uint[] _Bic_Orr_Vi_16bit_() { return new[] { 0x2F009400u, // BIC V0.4H, #0 - 0x0F009400u // ORR V0.4H, #0 + 0x0F009400u, // ORR V0.4H, #0 }; } @@ -104,7 +108,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x2F001400u, // BIC V0.2S, #0 - 0x0F001400u // ORR V0.2S, #0 + 0x0F001400u, // ORR V0.2S, #0 }; } @@ -112,7 +116,7 @@ namespace Ryujinx.Tests.Cpu { return new[] { - 0x0F00F400u // FMOV V0.2S, #2.0 + 0x0F00F400u, // FMOV V0.2S, #2.0 }; } @@ -120,7 +124,7 @@ namespace Ryujinx.Tests.Cpu { return new[] { - 0x4F00F400u // FMOV V0.4S, #2.0 + 0x4F00F400u, // FMOV V0.4S, #2.0 }; } @@ -128,7 +132,7 @@ namespace Ryujinx.Tests.Cpu { return new[] { - 0x6F00F400u // FMOV V0.2D, #2.0 + 0x6F00F400u, // FMOV V0.2D, #2.0 }; } @@ -136,7 +140,7 @@ namespace Ryujinx.Tests.Cpu { return new[] { - 0x0F00E400u // MOVI V0.8B, #0 + 0x0F00E400u, // MOVI V0.8B, #0 }; } @@ -145,7 +149,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x0F008400u, // MOVI V0.4H, #0 - 0x2F008400u // MVNI V0.4H, #0 + 0x2F008400u, // MVNI V0.4H, #0 }; } @@ -154,7 +158,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x0F000400u, // MOVI V0.2S, #0 - 0x2F000400u // MVNI V0.2S, #0 + 0x2F000400u, // MVNI V0.2S, #0 }; } @@ -163,7 +167,7 @@ namespace Ryujinx.Tests.Cpu return new[] { 0x0F00C400u, // MOVI V0.2S, #0, MSL #8 - 0x2F00C400u // MVNI V0.2S, #0, MSL #8 + 0x2F00C400u, // MVNI V0.2S, #0, MSL #8 }; } @@ -171,7 +175,7 @@ namespace Ryujinx.Tests.Cpu { return new[] { - 0x2F00E400u // MOVI D0, #0 + 0x2F00E400u, // MOVI D0, #0 }; } @@ -179,12 +183,12 @@ namespace Ryujinx.Tests.Cpu { return new[] { - 0x6F00E400u // MOVI V0.2D, #0 + 0x6F00E400u, // MOVI V0.2D, #0 }; } -#endregion + #endregion - private const int RndCntImm8 = 2; + private const int RndCntImm8 = 2; private const int RndCntImm64 = 2; [Test, Pairwise] @@ -194,7 +198,7 @@ namespace Ryujinx.Tests.Cpu [Values(0b0u, 0b1u)] uint amount, // <0, 8> [Values(0b0u, 0b1u)] uint q) // <4H, 8H> { - uint abc = (imm8 & 0xE0u) >> 5; + uint abc = (imm8 & 0xE0u) >> 5; uint defgh = (imm8 & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -215,7 +219,7 @@ namespace Ryujinx.Tests.Cpu [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24> [Values(0b0u, 0b1u)] uint q) // <2S, 4S> { - uint abc = (imm8 & 0xE0u) >> 5; + uint abc = (imm8 & 0xE0u) >> 5; uint defgh = (imm8 & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -229,11 +233,12 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Mov_Vi_2S([ValueSource(nameof(_F_Mov_Vi_2S_))] uint opcodes, [Range(0u, 255u, 1u)] uint abcdefgh) { - uint abc = (abcdefgh & 0xE0u) >> 5; + uint abc = (abcdefgh & 0xE0u) >> 5; uint defgh = (abcdefgh & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -246,11 +251,12 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Mov_Vi_4S([ValueSource(nameof(_F_Mov_Vi_4S_))] uint opcodes, [Range(0u, 255u, 1u)] uint abcdefgh) { - uint abc = (abcdefgh & 0xE0u) >> 5; + uint abc = (abcdefgh & 0xE0u) >> 5; uint defgh = (abcdefgh & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -260,11 +266,12 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise] [Explicit] + [Test, Pairwise] + [Explicit] public void F_Mov_Vi_2D([ValueSource(nameof(_F_Mov_Vi_2D_))] uint opcodes, [Range(0u, 255u, 1u)] uint abcdefgh) { - uint abc = (abcdefgh & 0xE0u) >> 5; + uint abc = (abcdefgh & 0xE0u) >> 5; uint defgh = (abcdefgh & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -279,7 +286,7 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_8BIT_IMM_))] byte imm8, [Values(0b0u, 0b1u)] uint q) // <8B, 16B> { - uint abc = (imm8 & 0xE0u) >> 5; + uint abc = (imm8 & 0xE0u) >> 5; uint defgh = (imm8 & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -299,7 +306,7 @@ namespace Ryujinx.Tests.Cpu [Values(0b0u, 0b1u)] uint amount, // <0, 8> [Values(0b0u, 0b1u)] uint q) // <4H, 8H> { - uint abc = (imm8 & 0xE0u) >> 5; + uint abc = (imm8 & 0xE0u) >> 5; uint defgh = (imm8 & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -320,7 +327,7 @@ namespace Ryujinx.Tests.Cpu [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24> [Values(0b0u, 0b1u)] uint q) // <2S, 4S> { - uint abc = (imm8 & 0xE0u) >> 5; + uint abc = (imm8 & 0xE0u) >> 5; uint defgh = (imm8 & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -341,7 +348,7 @@ namespace Ryujinx.Tests.Cpu [Values(0b0u, 0b1u)] uint amount, // <8, 16> [Values(0b0u, 0b1u)] uint q) // <2S, 4S> { - uint abc = (imm8 & 0xE0u) >> 5; + uint abc = (imm8 & 0xE0u) >> 5; uint defgh = (imm8 & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -362,7 +369,7 @@ namespace Ryujinx.Tests.Cpu { byte imm8 = ShrinkImm64(imm); - uint abc = (imm8 & 0xE0u) >> 5; + uint abc = (imm8 & 0xE0u) >> 5; uint defgh = (imm8 & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -381,7 +388,7 @@ namespace Ryujinx.Tests.Cpu { byte imm8 = ShrinkImm64(imm); - uint abc = (imm8 & 0xE0u) >> 5; + uint abc = (imm8 & 0xE0u) >> 5; uint defgh = (imm8 & 0x1Fu); opcodes |= (abc << 16) | (defgh << 5); @@ -392,4 +399,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -}
\ No newline at end of file +} |