diff options
| author | TSRBerry <20988865+TSRBerry@users.noreply.github.com> | 2023-07-01 04:14:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-07-01 02:14:34 +0000 |
| commit | e9848339ddac3d6fe32a0ce0fbe6029c4ad40429 (patch) | |
| tree | 8674ac269970ae79efca9a080ec626a62918505e /src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs | |
| parent | 6e28a4dd13df0ab866e6a178086abe36ca4a2b25 (diff) | |
[Ryujinx.Tests] Address dotnet-format issues (#5389)1.1.943
* dotnet format style --severity info
Some changes were manually reverted.
* dotnet format analyzers --serverity info
Some changes have been minimally adapted.
* Restore a few unused methods and variables
* Fix new dotnet-format issues after rebase
* Address review comments
* Address most dotnet format whitespace warnings
* Apply dotnet format whitespace formatting
A few of them have been manually reverted and the corresponding warning was silenced
* Format if-blocks correctly
* Run dotnet format after rebase and remove unused usings
- analyzers
- style
- whitespace
* Add comments to disabled warnings
* Simplify properties and array initialization, Use const when possible, Remove trailing commas
* cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress
* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"
This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.
* dotnet format whitespace after rebase
* Apply suggestions from code review
Co-authored-by: Ac_K <Acoustik666@gmail.com>
* First dotnet format pass
* Fix naming rule violations
* Remove naming rule violation exceptions
* Fix comment style
* Use targeted new
* Remove redundant code
* Remove comment alignment
* Remove naming rule exceptions
* Add trailing commas
* Use nameof expression
* Reformat to add remaining trailing commas
---------
Co-authored-by: Ac_K <Acoustik666@gmail.com>
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs | 73 |
1 files changed, 40 insertions, 33 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs index 42bc2ac5..6087a683 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs @@ -11,14 +11,14 @@ namespace Ryujinx.Tests.Cpu { #if Simd32 -#region "ValueSource (Opcodes)" + #region "ValueSource (Opcodes)" private static uint[] _Vabs_Vneg_Vpaddl_I_() { return new[] { 0xf3b10300u, // VABS.S8 D0, D0 0xf3b10380u, // VNEG.S8 D0, D0 - 0xf3b00200u // VPADDL.S8 D0, D0 + 0xf3b00200u, // VPADDL.S8 D0, D0 }; } @@ -27,18 +27,20 @@ namespace Ryujinx.Tests.Cpu return new[] { 0xf3b90700u, // VABS.F32 D0, D0 - 0xf3b90780u // VNEG.F32 D0, D0 + 0xf3b90780u, // VNEG.F32 D0, D0 }; } -#endregion + #endregion -#region "ValueSource (Types)" + #region "ValueSource (Types)" private static ulong[] _8B4H2S_() { - return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, - 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, - 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, - 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; + return new[] { + 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, + 0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul, + }; } private static IEnumerable<ulong> _1S_F_() @@ -52,19 +54,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x00000000007FFFFFul; // +Max Subnormal yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x0000000080000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0x00000000FF800000ul; // -Infinity yield return 0x000000007F800000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN) yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload) @@ -94,19 +96,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x007FFFFF007FFFFFul; // +Max Subnormal yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x8000000080000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0xFF800000FF800000ul; // -Infinity yield return 0x7F8000007F800000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN) yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones payload) @@ -135,19 +137,19 @@ namespace Ryujinx.Tests.Cpu yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon) - if (!NoZeros) + if (!_noZeros) { yield return 0x8000000000000000ul; // -Zero yield return 0x0000000000000000ul; // +Zero } - if (!NoInfs) + if (!_noInfs) { yield return 0xFFF0000000000000ul; // -Infinity yield return 0x7FF0000000000000ul; // +Infinity } - if (!NoNaNs) + if (!_noNaNs) { yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN) yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones payload) @@ -173,13 +175,13 @@ namespace Ryujinx.Tests.Cpu (cnt << 24) | (cnt << 16) | (cnt << 08) | cnt; } } -#endregion + #endregion private const int RndCnt = 2; - private static readonly bool NoZeros = false; - private static readonly bool NoInfs = false; - private static readonly bool NoNaNs = false; + private static readonly bool _noZeros = false; + private static readonly bool _noInfs = false; + private static readonly bool _noNaNs = false; [Test, Pairwise, Description("SHA256SU0.32 <Qd>, <Qm>")] public void Sha256su0_V([Values(0xF3BA03C0u)] uint opcode, @@ -193,7 +195,7 @@ namespace Ryujinx.Tests.Cpu [Values(0x74CED221E2793F07ul)] ulong resultH) { opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); V128 v0 = MakeVectorE0E1(z0, z1); V128 v1 = MakeVectorE0E1(a0, a1); @@ -223,12 +225,14 @@ namespace Ryujinx.Tests.Cpu { opcode |= 1 << 6; - rd >>= 1; rd <<= 1; - rm >>= 1; rm <<= 1; + rd >>= 1; + rd <<= 1; + rm >>= 1; + rm <<= 1; } opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= (size & 0x3) << 18; @@ -252,12 +256,14 @@ namespace Ryujinx.Tests.Cpu { opcode |= 1 << 6; - rd >>= 1; rd <<= 1; - rm >>= 1; rm <<= 1; + rd >>= 1; + rd <<= 1; + rm >>= 1; + rm <<= 1; } opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); V128 v0 = MakeVectorE0E1(z, ~z); V128 v1 = MakeVectorE0E1(b, ~b); @@ -286,7 +292,7 @@ namespace Ryujinx.Tests.Cpu } opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); V128 v0 = MakeVectorE0E1(d0, d1); @@ -303,12 +309,13 @@ namespace Ryujinx.Tests.Cpu [Values(0u, 1u, 2u, 3u)] uint op, [Values(0u, 1u, 2u)] uint size) // <S8, S16, S32> { - rm >>= 1; rm <<= 1; + rm >>= 1; + rm <<= 1; uint opcode = 0xf3b20200u; // VMOVN.S16 D0, Q0 opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); opcode |= (op & 0x3) << 6; opcode |= (size & 0x3) << 18; @@ -322,4 +329,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -}
\ No newline at end of file +} |