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authorTSR Berry <20988865+TSRBerry@users.noreply.github.com>2023-04-08 01:22:00 +0200
committerMary <thog@protonmail.com>2023-04-27 23:51:14 +0200
commitcee712105850ac3385cd0091a923438167433f9f (patch)
tree4a5274b21d8b7f938c0d0ce18736d3f2993b11b1 /src/Ryujinx.Graphics.Gpu/Engine/GPFifo/CompressedMethod.cs
parentcd124bda587ef09668a971fa1cac1c3f0cfc9f21 (diff)
Move solution and projects to src
Diffstat (limited to 'src/Ryujinx.Graphics.Gpu/Engine/GPFifo/CompressedMethod.cs')
-rw-r--r--src/Ryujinx.Graphics.Gpu/Engine/GPFifo/CompressedMethod.cs41
1 files changed, 41 insertions, 0 deletions
diff --git a/src/Ryujinx.Graphics.Gpu/Engine/GPFifo/CompressedMethod.cs b/src/Ryujinx.Graphics.Gpu/Engine/GPFifo/CompressedMethod.cs
new file mode 100644
index 00000000..458dc8f6
--- /dev/null
+++ b/src/Ryujinx.Graphics.Gpu/Engine/GPFifo/CompressedMethod.cs
@@ -0,0 +1,41 @@
+// This file was auto-generated from NVIDIA official Maxwell definitions.
+
+namespace Ryujinx.Graphics.Gpu.Engine.GPFifo
+{
+ enum TertOp
+ {
+ Grp0IncMethod = 0,
+ Grp0SetSubDevMask = 1,
+ Grp0StoreSubDevMask = 2,
+ Grp0UseSubDevMask = 3,
+ Grp2NonIncMethod = 0
+ }
+
+ enum SecOp
+ {
+ Grp0UseTert = 0,
+ IncMethod = 1,
+ Grp2UseTert = 2,
+ NonIncMethod = 3,
+ ImmdDataMethod = 4,
+ OneInc = 5,
+ Reserved6 = 6,
+ EndPbSegment = 7
+ }
+
+ struct CompressedMethod
+ {
+#pragma warning disable CS0649
+ public uint Method;
+#pragma warning restore CS0649
+ public int MethodAddressOld => (int)((Method >> 2) & 0x7FF);
+ public int MethodAddress => (int)((Method >> 0) & 0xFFF);
+ public int SubdeviceMask => (int)((Method >> 4) & 0xFFF);
+ public int MethodSubchannel => (int)((Method >> 13) & 0x7);
+ public TertOp TertOp => (TertOp)((Method >> 16) & 0x3);
+ public int MethodCountOld => (int)((Method >> 18) & 0x7FF);
+ public int MethodCount => (int)((Method >> 16) & 0x1FFF);
+ public int ImmdData => (int)((Method >> 16) & 0x1FFF);
+ public SecOp SecOp => (SecOp)((Method >> 29) & 0x7);
+ }
+}