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authorAc_K <Acoustik666@gmail.com>2024-01-30 00:51:05 +0100
committerGitHub <noreply@github.com>2024-01-30 00:51:05 +0100
commit8bf102d2cd744f56e2a4839fa0391acda3e201b8 (patch)
tree532c11f042b0811f6cf1179a46bfdcbf56393b26 /src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
parent2adf0318300a0f444c8051aceba1e4759fbedc6f (diff)
Cpu: Implement Vpadal and Vrintr instructions (#6185)1.1.1150
* Cpu: Implement Vpadal and Vrintr instructions This PR superseed last instructions left in #2242. Since I'm not a CPU guy I've just ported the code and nothing more. Please be precise during review if there are some changes to be done. It should fixes #1781 Co-Authored-By: Piyachet Kanda <piyachetk@gmail.com> * Addresses gdkchan's feedback * Addresses gdkchan's feedback 2 * Apply suggestions from code review Co-authored-by: gdkchan <gab.dark.100@gmail.com> * another fix * Update InstEmitSimdHelper32.cs * Correct fix * Addresses gdkchan's feedback * Update CpuTestSimdCvt32.cs --------- Co-authored-by: Piyachet Kanda <piyachetk@gmail.com> Co-authored-by: gdkchan <gab.dark.100@gmail.com>
Diffstat (limited to 'src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs')
-rw-r--r--src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
index c1c59b87..2f021a1a 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
@@ -673,6 +673,35 @@ namespace ARMeilleure.Instructions
context.Copy(GetVecA32(op.Qd), res);
}
+ public static void EmitVectorPairwiseTernaryLongOpI32(ArmEmitterContext context, Func3I emit, bool signed)
+ {
+ OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+ int elems = op.GetBytesCount() >> op.Size;
+ int pairs = elems >> 1;
+
+ Operand res = GetVecA32(op.Qd);
+
+ for (int index = 0; index < pairs; index++)
+ {
+ int pairIndex = index * 2;
+ Operand m1 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex, op.Size, signed);
+ Operand m2 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex + 1, op.Size, signed);
+
+ if (op.Size == 2)
+ {
+ m1 = signed ? context.SignExtend32(OperandType.I64, m1) : context.ZeroExtend32(OperandType.I64, m1);
+ m2 = signed ? context.SignExtend32(OperandType.I64, m2) : context.ZeroExtend32(OperandType.I64, m2);
+ }
+
+ Operand d1 = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size + 1, signed);
+
+ res = EmitVectorInsert(context, res, emit(m1, m2, d1), op.Id + index, op.Size + 1);
+ }
+
+ context.Copy(GetVecA32(op.Qd), res);
+ }
+
// Narrow
public static void EmitVectorUnaryNarrowOp32(ArmEmitterContext context, Func1I emit, bool signed = false)