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| author | gdkchan <gab.dark.100@gmail.com> | 2018-02-10 14:20:46 -0300 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-02-10 14:20:46 -0300 |
| commit | 55743c0cba7d1f3daafcedff4f9f623fdcf24b83 (patch) | |
| tree | 6f2257fff3925a8887de90aebeb003be68241d8b /Ryujinx/Cpu/Decoder/AOpCodeSimd.cs | |
| parent | 9f612682e0026a82f13e28b0e3b610e129ee98a5 (diff) | |
Only throw undefined instruction exception at execution, not at translation stage
Diffstat (limited to 'Ryujinx/Cpu/Decoder/AOpCodeSimd.cs')
| -rw-r--r-- | Ryujinx/Cpu/Decoder/AOpCodeSimd.cs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Ryujinx/Cpu/Decoder/AOpCodeSimd.cs b/Ryujinx/Cpu/Decoder/AOpCodeSimd.cs index 79619984..5f940b22 100644 --- a/Ryujinx/Cpu/Decoder/AOpCodeSimd.cs +++ b/Ryujinx/Cpu/Decoder/AOpCodeSimd.cs @@ -12,7 +12,7 @@ namespace ChocolArm64.Decoder public int SizeF => Size & 1; - public AOpCodeSimd(AInst Inst, long Position, int OpCode) : base(Inst, Position) + public AOpCodeSimd(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode) { Rd = (OpCode >> 0) & 0x1f; Rn = (OpCode >> 5) & 0x1f; |