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| author | gdkchan <gab.dark.100@gmail.com> | 2020-03-10 21:49:27 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-11 11:49:27 +1100 |
| commit | c26f3774bdbf3982149a3ea4c0f7abb4de869db7 (patch) | |
| tree | 45805ff76e7a4f486d5132d39ec7f901f462adcb /Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs | |
| parent | 89ccec197ec9a5db2bb308ef3e9178910d1ab7a8 (diff) | |
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes
* Re-align opcode table
* Re-enable undefined, use subclasses to fix checks
* Add test and fix VRSHR instruction
* PR feedback
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs | 94 |
1 files changed, 80 insertions, 14 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs index 6c7b0493..aad4a2a5 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs @@ -11,17 +11,19 @@ namespace Ryujinx.Tests.Cpu #if SimdShImm32 private const int RndCnt = 2; - [Test, Pairwise, Description("VSHL.<size> {<Vd>}, <Vm>, #<imm>")] - public void Vshl_Imm([Values(0u)] uint rd, + [Test, Pairwise] + public void Vrshr_Vshr_Imm([Values(0u)] uint rd, [Values(2u, 0u)] uint rm, [Values(0u, 1u, 2u, 3u)] uint size, [Random(RndCnt), Values(0u)] uint shiftImm, [Random(RndCnt)] ulong z, [Random(RndCnt)] ulong a, [Random(RndCnt)] ulong b, - [Values] bool q) + [Values] bool u, + [Values] bool q, + [Values] bool round) { - uint opcode = 0xf2800510u; // VORR.I32 D0, #0 (immediate value changes it into SHL) + uint opcode = 0xf2800010u; // VMOV.I32 D0, #0 (immediate value changes it into SHR) if (q) { opcode |= 1 << 6; @@ -29,6 +31,16 @@ namespace Ryujinx.Tests.Cpu rd <<= 1; } + if (round) + { + opcode |= 1 << 9; // Turn into VRSHR + } + + if (u) + { + opcode |= 1 << 24; + } + uint imm = 1u << ((int)size + 3); imm |= shiftImm & (imm - 1); @@ -45,18 +57,17 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise, Description("VSHR.<size> {<Vd>}, <Vm>, #<imm>")] - public void Vshr_Imm([Values(0u)] uint rd, + [Test, Pairwise, Description("VSHL.<size> {<Vd>}, <Vm>, #<imm>")] + public void Vshl_Imm([Values(0u)] uint rd, [Values(2u, 0u)] uint rm, [Values(0u, 1u, 2u, 3u)] uint size, [Random(RndCnt), Values(0u)] uint shiftImm, [Random(RndCnt)] ulong z, [Random(RndCnt)] ulong a, [Random(RndCnt)] ulong b, - [Values] bool u, [Values] bool q) { - uint opcode = 0xf2800010u; // VMOV.I32 D0, #0 (immediate value changes it into SHR) + uint opcode = 0xf2800510u; // VORR.I32 D0, #0 (immediate value changes it into SHL) if (q) { opcode |= 1 << 6; @@ -64,11 +75,6 @@ namespace Ryujinx.Tests.Cpu rd <<= 1; } - if (u) - { - opcode |= 1 << 24; - } - uint imm = 1u << ((int)size + 3); imm |= shiftImm & (imm - 1); @@ -85,7 +91,7 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise, Description("VSHRN.<size> {<Vd>}, <Vm>, #<imm>")] + [Test, Pairwise, Description("VSHRN.<size> <Vd>, <Vm>, #<imm>")] public void Vshrn_Imm([Values(0u, 1u)] uint rd, [Values(2u, 0u)] uint rm, [Values(0u, 1u, 2u)] uint size, @@ -111,6 +117,66 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } + + [Test, Pairwise, Description("VQRSHRN.<type><size> <Vd>, <Vm>, #<imm>")] + public void Vqrshrn_Imm([Values(0u, 1u)] uint rd, + [Values(2u, 0u)] uint rm, + [Values(0u, 1u, 2u)] uint size, + [Random(RndCnt), Values(0u)] uint shiftImm, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] ulong a, + [Random(RndCnt)] ulong b, + [Values] bool u) + { + uint opcode = 0xf2800950u; // VORR.I16 Q0, #0 (immediate value changes it into QRSHRN) + + uint imm = 1u << ((int)size + 3); + imm |= shiftImm & (imm - 1); + + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); + opcode |= ((imm & 0x3f) << 16); + + if (u) + { + opcode |= 1u << 24; + } + + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(a, z); + V128 v2 = MakeVectorE0E1(b, z); + + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise, Description("VQRSHRUN.<type><size> <Vd>, <Vm>, #<imm>")] + public void Vqrshrun_Imm([Values(0u, 1u)] uint rd, + [Values(2u, 0u)] uint rm, + [Values(0u, 1u, 2u)] uint size, + [Random(RndCnt), Values(0u)] uint shiftImm, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] ulong a, + [Random(RndCnt)] ulong b) + { + uint opcode = 0xf3800850u; // VMOV.I16 Q0, #0x80 (immediate value changes it into QRSHRUN) + + uint imm = 1u << ((int)size + 3); + imm |= shiftImm & (imm - 1); + + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); + opcode |= ((imm & 0x3f) << 16); + + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(a, z); + V128 v2 = MakeVectorE0E1(b, z); + + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + + CompareAgainstUnicorn(); + } #endif } } |