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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-08-08 17:18:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-08 17:18:51 +0200 |
| commit | e36e97c64d7b973fbbc3ac92e9f115d74a4d9e2d (patch) | |
| tree | 80bdb45273e6bbc0d862276bdb6f6551b0a2541d /Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs | |
| parent | 8d59ad88b4d59ef6ad26b9a747dc871fd1f1007a (diff) | |
CPU: This PR fixes Fpscr, among other things. (#1433)
* CPU: This PR fixes Fpscr, among other things.
* Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.
* Fix Vcmp & Vcmpe opcode table.
* Revert "Fix Vcmp & Vcmpe opcode table."
This reverts commit c117d9410d693185ff5f8ee8e457ffbfb2027dd5.
* Address PR feedbacks.
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs index cd93cb16..a8c32d58 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs @@ -173,7 +173,7 @@ namespace Ryujinx.Tests.Cpu public void Vshl_Imm([Values(0u)] uint rd, [Values(2u, 0u)] uint rm, [Values(0u, 1u, 2u, 3u)] uint size, - [Random(RndCnt), Values(0u)] uint shiftImm, + [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm, [Random(RndCnt)] ulong z, [Random(RndCnt)] ulong a, [Random(RndCnt)] ulong b, @@ -207,7 +207,7 @@ namespace Ryujinx.Tests.Cpu public void Vshrn_Imm([Values(0u, 1u)] uint rd, [Values(2u, 0u)] uint rm, [Values(0u, 1u, 2u)] uint size, - [Random(RndCnt), Values(0u)] uint shiftImm, + [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm, [Random(RndCnt)] ulong z, [Random(RndCnt)] ulong a, [Random(RndCnt)] ulong b) @@ -234,7 +234,7 @@ namespace Ryujinx.Tests.Cpu public void Vqrshrn_Imm([Values(0u, 1u)] uint rd, [Values(2u, 0u)] uint rm, [Values(0u, 1u, 2u)] uint size, - [Random(RndCnt), Values(0u)] uint shiftImm, + [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm, [Random(RndCnt)] ulong z, [Random(RndCnt)] ulong a, [Random(RndCnt)] ulong b, @@ -258,16 +258,18 @@ namespace Ryujinx.Tests.Cpu V128 v1 = MakeVectorE0E1(a, z); V128 v2 = MakeVectorE0E1(b, z); - SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc; - CompareAgainstUnicorn(); + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr); + + CompareAgainstUnicorn(fpsrMask: Fpsr.Qc); } [Test, Pairwise, Description("VQRSHRUN.<type><size> <Vd>, <Vm>, #<imm>")] public void Vqrshrun_Imm([Values(0u, 1u)] uint rd, [Values(2u, 0u)] uint rm, [Values(0u, 1u, 2u)] uint size, - [Random(RndCnt), Values(0u)] uint shiftImm, + [Random(RndCntShiftImm)] [Values(0u)] uint shiftImm, [Random(RndCnt)] ulong z, [Random(RndCnt)] ulong a, [Random(RndCnt)] ulong b) @@ -285,9 +287,11 @@ namespace Ryujinx.Tests.Cpu V128 v1 = MakeVectorE0E1(a, z); V128 v2 = MakeVectorE0E1(b, z); - SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + int fpscr = (int)TestContext.CurrentContext.Random.NextUInt() & (int)Fpsr.Qc; - CompareAgainstUnicorn(); + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr); + + CompareAgainstUnicorn(fpsrMask: Fpsr.Qc); } #endif } |