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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2021-03-25 23:33:32 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-25 23:33:32 +0100 |
| commit | 4bd1ad16f93e8decf790191868690c3bd3875ee0 (patch) | |
| tree | ffbb5f3e76465f74bcd3d397ac53d36a76256986 /Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs | |
| parent | 53b9267b47a1541d596b763894c75fdecf5698e9 (diff) | |
Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs | 60 |
1 files changed, 32 insertions, 28 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs b/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs index 23e0e364..5d0a8f3f 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs @@ -26,23 +26,27 @@ namespace Ryujinx.Tests.Cpu #endregion #region "ValueSource (Opcodes)" - private static uint[] _Mla_Mls_Mul_Ve_4H_8H_() + private static uint[] _Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_4H_8H_() { return new uint[] { - 0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0] - 0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0] - 0x0F408000u // MUL V0.4H, V0.4H, V0.H[0] + 0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0] + 0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0] + 0x0F408000u, // MUL V0.4H, V0.4H, V0.H[0] + 0x0F40C000u, // SQDMULH V0.4H, V0.4H, V0.H[0] + 0x0F40D000u // SQRDMULH V0.4H, V0.4H, V0.H[0] }; } - private static uint[] _Mla_Mls_Mul_Ve_2S_4S_() + private static uint[] _Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_2S_4S_() { return new uint[] { - 0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0] - 0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0] - 0x0F808000u // MUL V0.2S, V0.2S, V0.S[0] + 0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0] + 0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0] + 0x0F808000u, // MUL V0.2S, V0.2S, V0.S[0] + 0x0F80C000u, // SQDMULH V0.2S, V0.2S, V0.S[0] + 0x0F80D000u // SQRDMULH V0.2S, V0.2S, V0.S[0] }; } @@ -77,15 +81,15 @@ namespace Ryujinx.Tests.Cpu private const int RndCntIndex = 2; [Test, Pairwise] - public void Mla_Mls_Mul_Ve_4H_8H([ValueSource("_Mla_Mls_Mul_Ve_4H_8H_")] uint opcodes, - [Values(0u)] uint rd, - [Values(1u, 0u)] uint rn, - [Values(2u, 0u)] uint rm, - [ValueSource("_4H_")] [Random(RndCnt)] ulong z, - [ValueSource("_4H_")] [Random(RndCnt)] ulong a, - [ValueSource("_4H_")] [Random(RndCnt)] ulong b, - [Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index, - [Values(0b0u, 0b1u)] uint q) // <4H, 8H> + public void Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_4H_8H([ValueSource(nameof(_Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_4H_8H_))] uint opcodes, + [Values(0u)] uint rd, + [Values(1u, 0u)] uint rn, + [Values(2u, 0u)] uint rm, + [ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong z, + [ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong a, + [ValueSource(nameof(_4H_))] [Random(RndCnt)] ulong b, + [Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index, + [Values(0b0u, 0b1u)] uint q) // <4H, 8H> { uint h = (index >> 2) & 1; uint l = (index >> 1) & 1; @@ -101,19 +105,19 @@ namespace Ryujinx.Tests.Cpu SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(fpsrMask: Fpsr.Qc); } [Test, Pairwise] - public void Mla_Mls_Mul_Ve_2S_4S([ValueSource("_Mla_Mls_Mul_Ve_2S_4S_")] uint opcodes, - [Values(0u)] uint rd, - [Values(1u, 0u)] uint rn, - [Values(2u, 0u)] uint rm, - [ValueSource("_2S_")] [Random(RndCnt)] ulong z, - [ValueSource("_2S_")] [Random(RndCnt)] ulong a, - [ValueSource("_2S_")] [Random(RndCnt)] ulong b, - [Values(0u, 1u, 2u, 3u)] uint index, - [Values(0b0u, 0b1u)] uint q) // <2S, 4S> + public void Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_2S_4S([ValueSource(nameof(_Mla_Mls_Mul_Sqdmulh_Sqrdmulh_Ve_2S_4S_))] uint opcodes, + [Values(0u)] uint rd, + [Values(1u, 0u)] uint rn, + [Values(2u, 0u)] uint rm, + [ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong z, + [ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong a, + [ValueSource(nameof(_2S_))] [Random(RndCnt)] ulong b, + [Values(0u, 1u, 2u, 3u)] uint index, + [Values(0b0u, 0b1u)] uint q) // <2S, 4S> { uint h = (index >> 1) & 1; uint l = index & 1; @@ -128,7 +132,7 @@ namespace Ryujinx.Tests.Cpu SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(fpsrMask: Fpsr.Qc); } [Test, Pairwise] |