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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2018-10-14 04:35:16 +0200
committergdkchan <gab.dark.100@gmail.com>2018-10-13 23:35:16 -0300
commit894459fcd7797b1e38f2448797d83856d11b6e23 (patch)
tree87a67e3b80cba4b05a29d243db63d130e1b362c2 /Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs
parentac1a379265d0c02a8bd4a146c205f21e2d00f3ab (diff)
Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)
* Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs * Update ASoftFallback.cs * Update ASoftFloat.cs * Update AOpCodeSimdRegElemF.cs * Update CpuTestSimdIns.cs * Update CpuTestSimdRegElem.cs * Create CpuTestSimdRegElemF.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Superseded Fmul_Se Test. Nit. * Address PR feedback. * Address PR feedback. * Update AInstEmitSimdArithmetic.cs * Update ASoftFallback.cs * Update AInstEmitAlu.cs * Update AInstEmitSimdShift.cs
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs137
1 files changed, 52 insertions, 85 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs b/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs
index 4d14ab48..61552062 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs
@@ -13,7 +13,7 @@ namespace Ryujinx.Tests.Cpu
{
#if SimdRegElem
-#region "ValueSource"
+#region "ValueSource (Types)"
private static ulong[] _2S_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
@@ -27,114 +27,81 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
- private const int RndCnt = 2;
-
- [Test, Pairwise, Description("MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
- public void Mla_Ve_4H_8H([Values(0u)] uint Rd,
- [Values(1u, 0u)] uint Rn,
- [Values(2u, 0u)] uint Rm,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong A,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong B,
- [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index,
- [Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
+#region "ValueSource (Opcodes)"
+ private static uint[] _Mla_Mls_Mul_Ve_4H_8H_()
{
- uint H = (Index & 4) >> 2;
- uint L = (Index & 2) >> 1;
- uint M = (Index & 1) >> 0;
-
- uint Opcode = 0x2F400000; // MLA V0.4H, V0.4H, V0.H[0]
- Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
- Opcode |= (L << 21) | (M << 20) | (H << 11);
- Opcode |= ((Q & 1) << 30);
-
- Vector128<float> V0 = MakeVectorE0E1(Z, Z);
- Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
- Vector128<float> V2 = MakeVectorE0E1(B, B * H);
-
- AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
-
- CompareAgainstUnicorn();
+ return new uint[]
+ {
+ 0x2F400000u, // MLA V0.4H, V0.4H, V0.H[0]
+ 0x2F404000u, // MLS V0.4H, V0.4H, V0.H[0]
+ 0x0F408000u // MUL V0.4H, V0.4H, V0.H[0]
+ };
}
- [Test, Pairwise, Description("MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
- public void Mla_Ve_2S_4S([Values(0u)] uint Rd,
- [Values(1u, 0u)] uint Rn,
- [Values(2u, 0u)] uint Rm,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong A,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong B,
- [Values(0u, 1u, 2u, 3u)] uint Index,
- [Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
+ private static uint[] _Mla_Mls_Mul_Ve_2S_4S_()
{
- uint H = (Index & 2) >> 1;
- uint L = (Index & 1) >> 0;
-
- uint Opcode = 0x2F800000; // MLA V0.2S, V0.2S, V0.S[0]
- Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
- Opcode |= (L << 21) | (H << 11);
- Opcode |= ((Q & 1) << 30);
-
- Vector128<float> V0 = MakeVectorE0E1(Z, Z);
- Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
- Vector128<float> V2 = MakeVectorE0E1(B, B * H);
-
- AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
-
- CompareAgainstUnicorn();
+ return new uint[]
+ {
+ 0x2F800000u, // MLA V0.2S, V0.2S, V0.S[0]
+ 0x2F804000u, // MLS V0.2S, V0.2S, V0.S[0]
+ 0x0F808000u // MUL V0.2S, V0.2S, V0.S[0]
+ };
}
+#endregion
+
+ private const int RndCnt = 2;
- [Test, Pairwise, Description("MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
- public void Mls_Ve_4H_8H([Values(0u)] uint Rd,
- [Values(1u, 0u)] uint Rn,
- [Values(2u, 0u)] uint Rm,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong A,
- [ValueSource("_4H_")] [Random(RndCnt)] ulong B,
- [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index,
- [Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
+ [Test, Pairwise]
+ public void Mla_Mls_Mul_Ve_4H_8H([ValueSource("_Mla_Mls_Mul_Ve_4H_8H_")] uint Opcodes,
+ [Values(0u)] uint Rd,
+ [Values(1u, 0u)] uint Rn,
+ [Values(2u, 0u)] uint Rm,
+ [ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
+ [ValueSource("_4H_")] [Random(RndCnt)] ulong A,
+ [ValueSource("_4H_")] [Random(RndCnt)] ulong B,
+ [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index,
+ [Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
{
- uint H = (Index & 4) >> 2;
- uint L = (Index & 2) >> 1;
- uint M = (Index & 1) >> 0;
+ uint H = (Index >> 2) & 1;
+ uint L = (Index >> 1) & 1;
+ uint M = Index & 1;
- uint Opcode = 0x2F404000; // MLS V0.4H, V0.4H, V0.H[0]
- Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
- Opcode |= (L << 21) | (M << 20) | (H << 11);
- Opcode |= ((Q & 1) << 30);
+ Opcodes |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+ Opcodes |= (L << 21) | (M << 20) | (H << 11);
+ Opcodes |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H);
- AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+ AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
- public void Mls_Ve_2S_4S([Values(0u)] uint Rd,
- [Values(1u, 0u)] uint Rn,
- [Values(2u, 0u)] uint Rm,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong A,
- [ValueSource("_2S_")] [Random(RndCnt)] ulong B,
- [Values(0u, 1u, 2u, 3u)] uint Index,
- [Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
+ [Test, Pairwise]
+ public void Mla_Mls_Mul_Ve_2S_4S([ValueSource("_Mla_Mls_Mul_Ve_2S_4S_")] uint Opcodes,
+ [Values(0u)] uint Rd,
+ [Values(1u, 0u)] uint Rn,
+ [Values(2u, 0u)] uint Rm,
+ [ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
+ [ValueSource("_2S_")] [Random(RndCnt)] ulong A,
+ [ValueSource("_2S_")] [Random(RndCnt)] ulong B,
+ [Values(0u, 1u, 2u, 3u)] uint Index,
+ [Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
{
- uint H = (Index & 2) >> 1;
- uint L = (Index & 1) >> 0;
+ uint H = (Index >> 1) & 1;
+ uint L = Index & 1;
- uint Opcode = 0x2F804000; // MLS V0.2S, V0.2S, V0.S[0]
- Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
- Opcode |= (L << 21) | (H << 11);
- Opcode |= ((Q & 1) << 30);
+ Opcodes |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+ Opcodes |= (L << 21) | (H << 11);
+ Opcodes |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H);
- AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+ AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn();
}
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