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| author | sharmander <saldabain.dev@gmail.com> | 2020-12-16 18:27:15 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-16 20:27:15 -0300 |
| commit | e901b7850c74ee3650ef4ea887e4b43db36438c5 (patch) | |
| tree | 63db248391f7175216dcdbf7d68729eaad9e5370 /Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs | |
| parent | 61634dd415fb71b3ae85871a0873d00195b0900c (diff) | |
CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)
* Start implementation
* Draft
* Updated opcode.
Needs verification.
* Clean up code.
* Update implementation and tests.
* Update implemenation + tests
* Get RM from FPSCR + Do not use emit/addintrinsic
* Remove "fast" path, as recommended by gdk.
* Variable DELETED.
* Update ARMeilleure/Decoders/OpCodeTable.cs
Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
* Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs
Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
* Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs
Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
* Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs
Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
* Move method
* stringing things together :)
Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs index c25f2fa2..565d231a 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs @@ -2,6 +2,7 @@ using ARMeilleure.State; using NUnit.Framework; +using System; using System.Collections.Generic; namespace Ryujinx.Tests.Cpu @@ -215,6 +216,42 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } + + [Test, Pairwise, Description("VRINTX.F<size> <Sd>, <Sm>")] + public void Vrintx_S([Values(0u, 1u)] uint rd, + [Values(0u, 1u)] uint rm, + [Values(2u, 3u)] uint size, + [ValueSource(nameof(_1D_F_))] ulong s0, + [ValueSource(nameof(_1D_F_))] ulong s1, + [ValueSource(nameof(_1D_F_))] ulong s2, + [Values(RMode.Rn, RMode.Rm, RMode.Rp)] RMode rMode) + { + uint opcode = 0xEB70A40; + V128 v0, v1, v2; + if (size == 2) + { + opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5); + opcode |= ((rd & 0x1e) >> 11) | ((rm & 0x1) << 22); + v0 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s0), (uint)BitConverter.SingleToInt32Bits(s0)); + v1 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s1), (uint)BitConverter.SingleToInt32Bits(s0)); + v2 = MakeVectorE0E1((uint)BitConverter.SingleToInt32Bits(s2), (uint)BitConverter.SingleToInt32Bits(s1)); + } + else + { + opcode |= ((rm & 0xf) << 0) | ((rd & 0x10) << 1); + opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); + v0 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s0), (uint)BitConverter.DoubleToInt64Bits(s0)); + v1 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s1), (uint)BitConverter.DoubleToInt64Bits(s0)); + v2 = MakeVectorE0E1((uint)BitConverter.DoubleToInt64Bits(s2), (uint)BitConverter.DoubleToInt64Bits(s1)); + } + + opcode |= ((size & 3) << 8); + + int fpscr = (int)rMode << (int)Fpcr.RMode; + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr); + + CompareAgainstUnicorn(); + } #endif } } |