diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2019-08-08 15:56:22 -0300 |
|---|---|---|
| committer | emmauss <emmausssss@gmail.com> | 2019-08-08 21:56:22 +0300 |
| commit | a731ab3a2aad56e6ceb8b4e2444a61353246295c (patch) | |
| tree | c7f13f51bfec6b19431e62167811ae31e9d2fea9 /Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs | |
| parent | 1ba58e9942e54175e3f3a0e1d57a48537f4888b1 (diff) | |
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs | 64 |
1 files changed, 31 insertions, 33 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs index 4702b986..fd8ec9c5 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs @@ -1,11 +1,9 @@ // https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf -using ChocolArm64.State; +using ARMeilleure.State; using NUnit.Framework; -using System.Runtime.Intrinsics; - namespace Ryujinx.Tests.Cpu { public class CpuTestSimdCrypto : CpuTest @@ -23,20 +21,20 @@ namespace Ryujinx.Tests.Cpu uint opcode = 0x4E285800; // AESD V0.16B, V0.16B opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); - Vector128<float> v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH); - Vector128<float> v1 = MakeVectorE0E1(roundKeyL, roundKeyH); + V128 v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH); + V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH); - CpuThreadState threadState = SingleOpcode(opcode, v0: v0, v1: v1); + ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1); Assert.Multiple(() => { - Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL)); - Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH)); + Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL)); + Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH)); }); Assert.Multiple(() => { - Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(roundKeyL)); - Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(roundKeyH)); + Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(roundKeyL)); + Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(roundKeyH)); }); CompareAgainstUnicorn(); @@ -55,20 +53,20 @@ namespace Ryujinx.Tests.Cpu uint opcode = 0x4E284800; // AESE V0.16B, V0.16B opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); - Vector128<float> v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH); - Vector128<float> v1 = MakeVectorE0E1(roundKeyL, roundKeyH); + V128 v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH); + V128 v1 = MakeVectorE0E1(roundKeyL, roundKeyH); - CpuThreadState threadState = SingleOpcode(opcode, v0: v0, v1: v1); + ExecutionContext context = SingleOpcode(opcode, v0: v0, v1: v1); Assert.Multiple(() => { - Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL)); - Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH)); + Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL)); + Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH)); }); Assert.Multiple(() => { - Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(roundKeyL)); - Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(roundKeyH)); + Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(roundKeyL)); + Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(roundKeyH)); }); CompareAgainstUnicorn(); @@ -85,24 +83,24 @@ namespace Ryujinx.Tests.Cpu uint opcode = 0x4E287800; // AESIMC V0.16B, V0.16B opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); - Vector128<float> v = MakeVectorE0E1(valueL, valueH); + V128 v = MakeVectorE0E1(valueL, valueH); - CpuThreadState threadState = SingleOpcode( + ExecutionContext context = SingleOpcode( opcode, - v0: rn == 0u ? v : default(Vector128<float>), - v1: rn == 1u ? v : default(Vector128<float>)); + v0: rn == 0u ? v : default(V128), + v1: rn == 1u ? v : default(V128)); Assert.Multiple(() => { - Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL)); - Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH)); + Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL)); + Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH)); }); if (rn == 1u) { Assert.Multiple(() => { - Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(valueL)); - Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(valueH)); + Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(valueL)); + Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(valueH)); }); } @@ -120,24 +118,24 @@ namespace Ryujinx.Tests.Cpu uint opcode = 0x4E286800; // AESMC V0.16B, V0.16B opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); - Vector128<float> v = MakeVectorE0E1(valueL, valueH); + V128 v = MakeVectorE0E1(valueL, valueH); - CpuThreadState threadState = SingleOpcode( + ExecutionContext context = SingleOpcode( opcode, - v0: rn == 0u ? v : default(Vector128<float>), - v1: rn == 1u ? v : default(Vector128<float>)); + v0: rn == 0u ? v : default(V128), + v1: rn == 1u ? v : default(V128)); Assert.Multiple(() => { - Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL)); - Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH)); + Assert.That(GetVectorE0(context.GetV(0)), Is.EqualTo(resultL)); + Assert.That(GetVectorE1(context.GetV(0)), Is.EqualTo(resultH)); }); if (rn == 1u) { Assert.Multiple(() => { - Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(valueL)); - Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(valueH)); + Assert.That(GetVectorE0(context.GetV(1)), Is.EqualTo(valueL)); + Assert.That(GetVectorE1(context.GetV(1)), Is.EqualTo(valueH)); }); } |