diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-11-01 05:22:09 +0100 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-11-01 01:22:09 -0300 |
| commit | 1e7ea76f148660ff403938f3f84376879901e3ff (patch) | |
| tree | f01eece0c78b2946c80b885403005000ac1278a4 /Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs | |
| parent | 53e66645260e1dfe382138fa8ed09376da99cb60 (diff) | |
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
* Update SoftFloat.cs
* Update SoftFallback.cs
* Update InstEmitSimdShift.cs
* Update InstEmitSimdCvt.cs
* Update InstEmitSimdArithmetic.cs
* Update CryptoHelper.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuThreadState.cs
* Update OpCodeTable.cs
* Add files via upload
* Nit.
* Remove unused using. Nit.
* Remove unused using. FZ update.
* Nit.
* Remove unused using.
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs | 140 |
1 files changed, 70 insertions, 70 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs index ce2b50f0..4702b986 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs @@ -11,98 +11,98 @@ namespace Ryujinx.Tests.Cpu public class CpuTestSimdCrypto : CpuTest { [Test, Description("AESD <Vd>.16B, <Vn>.16B")] - public void Aesd_V([Values(0u)] uint Rd, - [Values(1u)] uint Rn, - [Values(0x7B5B546573745665ul)] ulong ValueH, - [Values(0x63746F725D53475Dul)] ulong ValueL, - [Random(2)] ulong RoundKeyH, - [Random(2)] ulong RoundKeyL, - [Values(0x8DCAB9BC035006BCul)] ulong ResultH, - [Values(0x8F57161E00CAFD8Dul)] ulong ResultL) + public void Aesd_V([Values(0u)] uint rd, + [Values(1u)] uint rn, + [Values(0x7B5B546573745665ul)] ulong valueH, + [Values(0x63746F725D53475Dul)] ulong valueL, + [Random(2)] ulong roundKeyH, + [Random(2)] ulong roundKeyL, + [Values(0x8DCAB9BC035006BCul)] ulong resultH, + [Values(0x8F57161E00CAFD8Dul)] ulong resultL) { - uint Opcode = 0x4E285800; // AESD V0.16B, V0.16B - Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + uint opcode = 0x4E285800; // AESD V0.16B, V0.16B + opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); - Vector128<float> V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH); - Vector128<float> V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH); + Vector128<float> v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH); + Vector128<float> v1 = MakeVectorE0E1(roundKeyL, roundKeyH); - CpuThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + CpuThreadState threadState = SingleOpcode(opcode, v0: v0, v1: v1); Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(ResultL)); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(ResultH)); + Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL)); + Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH)); }); Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL)); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH)); + Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(roundKeyL)); + Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(roundKeyH)); }); CompareAgainstUnicorn(); } [Test, Description("AESE <Vd>.16B, <Vn>.16B")] - public void Aese_V([Values(0u)] uint Rd, - [Values(1u)] uint Rn, - [Values(0x7B5B546573745665ul)] ulong ValueH, - [Values(0x63746F725D53475Dul)] ulong ValueL, - [Random(2)] ulong RoundKeyH, - [Random(2)] ulong RoundKeyL, - [Values(0x8F92A04DFBED204Dul)] ulong ResultH, - [Values(0x4C39B1402192A84Cul)] ulong ResultL) + public void Aese_V([Values(0u)] uint rd, + [Values(1u)] uint rn, + [Values(0x7B5B546573745665ul)] ulong valueH, + [Values(0x63746F725D53475Dul)] ulong valueL, + [Random(2)] ulong roundKeyH, + [Random(2)] ulong roundKeyL, + [Values(0x8F92A04DFBED204Dul)] ulong resultH, + [Values(0x4C39B1402192A84Cul)] ulong resultL) { - uint Opcode = 0x4E284800; // AESE V0.16B, V0.16B - Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + uint opcode = 0x4E284800; // AESE V0.16B, V0.16B + opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); - Vector128<float> V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH); - Vector128<float> V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH); + Vector128<float> v0 = MakeVectorE0E1(roundKeyL ^ valueL, roundKeyH ^ valueH); + Vector128<float> v1 = MakeVectorE0E1(roundKeyL, roundKeyH); - CpuThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + CpuThreadState threadState = SingleOpcode(opcode, v0: v0, v1: v1); Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(ResultL)); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(ResultH)); + Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL)); + Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH)); }); Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL)); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH)); + Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(roundKeyL)); + Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(roundKeyH)); }); CompareAgainstUnicorn(); } [Test, Description("AESIMC <Vd>.16B, <Vn>.16B")] - public void Aesimc_V([Values(0u)] uint Rd, - [Values(1u, 0u)] uint Rn, - [Values(0x8DCAB9DC035006BCul)] ulong ValueH, - [Values(0x8F57161E00CAFD8Dul)] ulong ValueL, - [Values(0xD635A667928B5EAEul)] ulong ResultH, - [Values(0xEEC9CC3BC55F5777ul)] ulong ResultL) + public void Aesimc_V([Values(0u)] uint rd, + [Values(1u, 0u)] uint rn, + [Values(0x8DCAB9DC035006BCul)] ulong valueH, + [Values(0x8F57161E00CAFD8Dul)] ulong valueL, + [Values(0xD635A667928B5EAEul)] ulong resultH, + [Values(0xEEC9CC3BC55F5777ul)] ulong resultL) { - uint Opcode = 0x4E287800; // AESIMC V0.16B, V0.16B - Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + uint opcode = 0x4E287800; // AESIMC V0.16B, V0.16B + opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); - Vector128<float> V = MakeVectorE0E1(ValueL, ValueH); + Vector128<float> v = MakeVectorE0E1(valueL, valueH); - CpuThreadState ThreadState = SingleOpcode( - Opcode, - V0: Rn == 0u ? V : default(Vector128<float>), - V1: Rn == 1u ? V : default(Vector128<float>)); + CpuThreadState threadState = SingleOpcode( + opcode, + v0: rn == 0u ? v : default(Vector128<float>), + v1: rn == 1u ? v : default(Vector128<float>)); Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(ResultL)); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(ResultH)); + Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL)); + Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH)); }); - if (Rn == 1u) + if (rn == 1u) { Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(ValueL)); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH)); + Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(valueL)); + Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(valueH)); }); } @@ -110,34 +110,34 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("AESMC <Vd>.16B, <Vn>.16B")] - public void Aesmc_V([Values(0u)] uint Rd, - [Values(1u, 0u)] uint Rn, - [Values(0x627A6F6644B109C8ul)] ulong ValueH, - [Values(0x2B18330A81C3B3E5ul)] ulong ValueL, - [Values(0x7B5B546573745665ul)] ulong ResultH, - [Values(0x63746F725D53475Dul)] ulong ResultL) + public void Aesmc_V([Values(0u)] uint rd, + [Values(1u, 0u)] uint rn, + [Values(0x627A6F6644B109C8ul)] ulong valueH, + [Values(0x2B18330A81C3B3E5ul)] ulong valueL, + [Values(0x7B5B546573745665ul)] ulong resultH, + [Values(0x63746F725D53475Dul)] ulong resultL) { - uint Opcode = 0x4E286800; // AESMC V0.16B, V0.16B - Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + uint opcode = 0x4E286800; // AESMC V0.16B, V0.16B + opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); - Vector128<float> V = MakeVectorE0E1(ValueL, ValueH); + Vector128<float> v = MakeVectorE0E1(valueL, valueH); - CpuThreadState ThreadState = SingleOpcode( - Opcode, - V0: Rn == 0u ? V : default(Vector128<float>), - V1: Rn == 1u ? V : default(Vector128<float>)); + CpuThreadState threadState = SingleOpcode( + opcode, + v0: rn == 0u ? v : default(Vector128<float>), + v1: rn == 1u ? v : default(Vector128<float>)); Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(ResultL)); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(ResultH)); + Assert.That(GetVectorE0(threadState.V0), Is.EqualTo(resultL)); + Assert.That(GetVectorE1(threadState.V0), Is.EqualTo(resultH)); }); - if (Rn == 1u) + if (rn == 1u) { Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(ValueL)); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH)); + Assert.That(GetVectorE0(threadState.V1), Is.EqualTo(valueL)); + Assert.That(GetVectorE1(threadState.V1), Is.EqualTo(valueH)); }); } |