aboutsummaryrefslogtreecommitdiff
path: root/Ryujinx.Tests/Cpu/CpuTestMisc.cs
diff options
context:
space:
mode:
authorgdkchan <gab.dark.100@gmail.com>2019-08-08 15:56:22 -0300
committeremmauss <emmausssss@gmail.com>2019-08-08 21:56:22 +0300
commita731ab3a2aad56e6ceb8b4e2444a61353246295c (patch)
treec7f13f51bfec6b19431e62167811ae31e9d2fea9 /Ryujinx.Tests/Cpu/CpuTestMisc.cs
parent1ba58e9942e54175e3f3a0e1d57a48537f4888b1 (diff)
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project * Refactoring around the old IRAdapter, now renamed to PreAllocator * Optimize the LowestBitSet method * Add CLZ support and fix CLS implementation * Add missing Equals and GetHashCode overrides on some structs, misc small tweaks * Implement the ByteSwap IR instruction, and some refactoring on the assembler * Implement the DivideUI IR instruction and fix 64-bits IDIV * Correct constant operand type on CSINC * Move division instructions implementation to InstEmitDiv * Fix destination type for the ConditionalSelect IR instruction * Implement UMULH and SMULH, with new IR instructions * Fix some issues with shift instructions * Fix constant types for BFM instructions * Fix up new tests using the new V128 struct * Update tests * Move DIV tests to a separate file * Add support for calls, and some instructions that depends on them * Start adding support for SIMD & FP types, along with some of the related ARM instructions * Fix some typos and the divide instruction with FP operands * Fix wrong method call on Clz_V * Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes * Implement SIMD logical instructions and more misc. fixes * Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations * Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes * Implement SIMD shift instruction and fix Dup_V * Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table * Fix check with tolerance on tester * Implement FP & SIMD comparison instructions, and some fixes * Update FCVT (Scalar) encoding on the table to support the Half-float variants * Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes * Use old memory access methods, made a start on SIMD memory insts support, some fixes * Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes * Fix arguments count with struct return values, other fixes * More instructions * Misc. fixes and integrate LDj3SNuD fixes * Update tests * Add a faster linear scan allocator, unwinding support on windows, and other changes * Update Ryujinx.HLE * Update Ryujinx.Graphics * Fix V128 return pointer passing, RCX is clobbered * Update Ryujinx.Tests * Update ITimeZoneService * Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks * Use generic GetFunctionPointerForDelegate method and other tweaks * Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics * Remove some unused code on the assembler * Fix REX.W prefix regression on float conversion instructions, add some sort of profiler * Add hardware capability detection * Fix regression on Sha1h and revert Fcm** changes * Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator * Fix silly mistake introduced on last commit on CpuId * Generate inline stack probes when the stack allocation is too large * Initial support for the System-V ABI * Support multiple destination operands * Fix SSE2 VectorInsert8 path, and other fixes * Change placement of XMM callee save and restore code to match other compilers * Rename Dest to Destination and Inst to Instruction * Fix a regression related to calls and the V128 type * Add an extra space on comments to match code style * Some refactoring * Fix vector insert FP32 SSE2 path * Port over the ARM32 instructions * Avoid memory protection races on JIT Cache * Another fix on VectorInsert FP32 (thanks to LDj3SNuD * Float operands don't need to use the same register when VEX is supported * Add a new register allocator, higher quality code for hot code (tier up), and other tweaks * Some nits, small improvements on the pre allocator * CpuThreadState is gone * Allow changing CPU emulators with a config entry * Add runtime identifiers on the ARMeilleure project * Allow switching between CPUs through a config entry (pt. 2) * Change win10-x64 to win-x64 on projects * Update the Ryujinx project to use ARMeilleure * Ensure that the selected register is valid on the hybrid allocator * Allow exiting on returns to 0 (should fix test regression) * Remove register assignments for most used variables on the hybrid allocator * Do not use fixed registers as spill temp * Add missing namespace and remove unneeded using * Address PR feedback * Fix types, etc * Enable AssumeStrictAbiCompliance by default * Ensure that Spill and Fill don't load or store any more than necessary
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestMisc.cs')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestMisc.cs82
1 files changed, 28 insertions, 54 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestMisc.cs b/Ryujinx.Tests/Cpu/CpuTestMisc.cs
index e976c2c0..6d2440c1 100644
--- a/Ryujinx.Tests/Cpu/CpuTestMisc.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestMisc.cs
@@ -1,11 +1,9 @@
#define Misc
-using ChocolArm64.State;
+using ARMeilleure.State;
using NUnit.Framework;
-using System.Runtime.Intrinsics.X86;
-
namespace Ryujinx.Tests.Cpu
{
[Category("Misc")]
@@ -32,10 +30,9 @@ namespace Ryujinx.Tests.Cpu
opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
opCset |= ((cond & 15) << 12);
- SetThreadState(x0: xn);
+ SetContext(x0: xn);
Opcode(opCmn);
Opcode(opCset);
- Opcode(0xD4200000); // BRK #0
Opcode(0xD65F03C0); // RET
ExecuteOpcodes();
@@ -58,10 +55,9 @@ namespace Ryujinx.Tests.Cpu
opCmn |= ((shift & 3) << 22) | ((imm & 4095) << 10);
opCset |= ((cond & 15) << 12);
- SetThreadState(x0: wn);
+ SetContext(x0: wn);
Opcode(opCmn);
Opcode(opCset);
- Opcode(0xD4200000); // BRK #0
Opcode(0xD65F03C0); // RET
ExecuteOpcodes();
@@ -84,10 +80,9 @@ namespace Ryujinx.Tests.Cpu
opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
opCset |= ((cond & 15) << 12);
- SetThreadState(x0: xn);
+ SetContext(x0: xn);
Opcode(opCmp);
Opcode(opCset);
- Opcode(0xD4200000); // BRK #0
Opcode(0xD65F03C0); // RET
ExecuteOpcodes();
@@ -110,10 +105,9 @@ namespace Ryujinx.Tests.Cpu
opCmp |= ((shift & 3) << 22) | ((imm & 4095) << 10);
opCset |= ((cond & 15) << 12);
- SetThreadState(x0: wn);
+ SetContext(x0: wn);
Opcode(opCmp);
Opcode(opCset);
- Opcode(0xD4200000); // BRK #0
Opcode(0xD65F03C0); // RET
ExecuteOpcodes();
@@ -136,11 +130,10 @@ namespace Ryujinx.Tests.Cpu
SUB W0, W0, #3
MUL W0, W1, W0
SDIV W0, W2, W0
- BRK #0
RET
*/
- SetThreadState(x0: a);
+ SetContext(x0: a);
Opcode(0x11000C02);
Opcode(0x51001401);
Opcode(0x1B017C42);
@@ -148,11 +141,10 @@ namespace Ryujinx.Tests.Cpu
Opcode(0x51000C00);
Opcode(0x1B007C20);
Opcode(0x1AC00C40);
- Opcode(0xD4200000);
Opcode(0xD65F03C0);
ExecuteOpcodes();
- Assert.That(GetThreadState().X0, Is.Zero);
+ Assert.That(GetContext().GetX(0), Is.Zero);
}
[Explicit]
@@ -185,24 +177,20 @@ namespace Ryujinx.Tests.Cpu
FADD S0, S0, S1
FDIV S0, S2, S0
FMUL S0, S0, S0
- BRK #0
RET
*/
- SetThreadState(
- v0: Sse.SetScalarVector128(a),
- v1: Sse.SetScalarVector128(b));
+ SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
Opcode(0x1E2E1002);
Opcode(0x1E201840);
Opcode(0x1E211841);
Opcode(0x1E212800);
Opcode(0x1E201840);
Opcode(0x1E200800);
- Opcode(0xD4200000);
Opcode(0xD65F03C0);
ExecuteOpcodes();
- Assert.That(Sse41.Extract(GetThreadState().V0, (byte)0), Is.EqualTo(16f));
+ Assert.That(GetContext().GetV(0).AsFloat(), Is.EqualTo(16f));
}
[Explicit]
@@ -235,24 +223,20 @@ namespace Ryujinx.Tests.Cpu
FADD D0, D0, D1
FDIV D0, D2, D0
FMUL D0, D0, D0
- BRK #0
RET
*/
- SetThreadState(
- v0: Sse.StaticCast<double, float>(Sse2.SetScalarVector128(a)),
- v1: Sse.StaticCast<double, float>(Sse2.SetScalarVector128(b)));
+ SetContext(v0: MakeVectorScalar(a), v1: MakeVectorScalar(b));
Opcode(0x1E6E1002);
Opcode(0x1E601840);
Opcode(0x1E611841);
Opcode(0x1E612800);
Opcode(0x1E601840);
Opcode(0x1E600800);
- Opcode(0xD4200000);
Opcode(0xD65F03C0);
ExecuteOpcodes();
- Assert.That(VectorExtractDouble(GetThreadState().V0, (byte)0), Is.EqualTo(16d));
+ Assert.That(GetContext().GetV(0).AsDouble(), Is.EqualTo(16d));
}
[Test, Ignore("The Tester supports only one return point.")]
@@ -279,9 +263,9 @@ namespace Ryujinx.Tests.Cpu
/*
0x0000000000001000: MOV W4, W0
- 0x0000000000001004: CBZ W0, #0x3C
+ 0x0000000000001004: CBZ W0, #0x34
0x0000000000001008: CMP W0, #1
- 0x000000000000100C: B.LS #0x48
+ 0x000000000000100C: B.LS #0x34
0x0000000000001010: MOVZ W2, #0x2
0x0000000000001014: MOVZ X1, #0x1
0x0000000000001018: MOVZ X3, #0
@@ -290,22 +274,19 @@ namespace Ryujinx.Tests.Cpu
0x0000000000001024: MOV X3, X1
0x0000000000001028: MOV X1, X0
0x000000000000102C: CMP W4, W2
- 0x0000000000001030: B.HS #0x1C
- 0x0000000000001034: BRK #0
- 0x0000000000001038: RET
- 0x000000000000103C: MOVZ X0, #0
- 0x0000000000001040: BRK #0
+ 0x0000000000001030: B.HS #-0x14
+ 0x0000000000001034: RET
+ 0x0000000000001038: MOVZ X0, #0
+ 0x000000000000103C: RET
+ 0x0000000000001040: MOVZ X0, #0x1
0x0000000000001044: RET
- 0x0000000000001048: MOVZ X0, #0x1
- 0x000000000000104C: BRK #0
- 0x0000000000001050: RET
*/
- SetThreadState(x0: a);
+ SetContext(x0: a);
Opcode(0x2A0003E4);
- Opcode(0x340001C0);
+ Opcode(0x340001A0);
Opcode(0x7100041F);
- Opcode(0x540001E9);
+ Opcode(0x540001A9);
Opcode(0x52800042);
Opcode(0xD2800021);
Opcode(0xD2800003);
@@ -315,17 +296,14 @@ namespace Ryujinx.Tests.Cpu
Opcode(0xAA0003E1);
Opcode(0x6B02009F);
Opcode(0x54FFFF62);
- Opcode(0xD4200000);
Opcode(0xD65F03C0);
Opcode(0xD2800000);
- Opcode(0xD4200000);
Opcode(0xD65F03C0);
Opcode(0xD2800020);
- Opcode(0xD4200000);
Opcode(0xD65F03C0);
ExecuteOpcodes();
- Assert.That(GetThreadState().X0, Is.EqualTo(Fn(a)));
+ Assert.That(GetContext().GetX(0), Is.EqualTo(Fn(a)));
}
[Explicit]
@@ -338,18 +316,16 @@ namespace Ryujinx.Tests.Cpu
0x0000000000001000: MOV X0, #2
0x0000000000001004: MOV X1, #3
0x0000000000001008: ADD X0, X0, X1
- 0x000000000000100C: BRK #0
- 0x0000000000001010: RET
+ 0x000000000000100C: RET
*/
Opcode(0xD2800040);
Opcode(0xD2800061);
Opcode(0x8B010000);
- Opcode(0xD4200000);
Opcode(0xD65F03C0);
ExecuteOpcodes();
- Assert.That(GetThreadState().X0, Is.EqualTo(result));
+ Assert.That(GetContext().GetX(0), Is.EqualTo(result));
Reset();
@@ -357,18 +333,16 @@ namespace Ryujinx.Tests.Cpu
0x0000000000001000: MOV X0, #3
0x0000000000001004: MOV X1, #2
0x0000000000001008: ADD X0, X0, X1
- 0x000000000000100C: BRK #0
- 0x0000000000001010: RET
+ 0x000000000000100C: RET
*/
Opcode(0xD2800060);
Opcode(0xD2800041);
Opcode(0x8B010000);
- Opcode(0xD4200000);
Opcode(0xD65F03C0);
ExecuteOpcodes();
- Assert.That(GetThreadState().X0, Is.EqualTo(result));
+ Assert.That(GetContext().GetX(0), Is.EqualTo(result));
}
[Explicit]
@@ -379,9 +353,9 @@ namespace Ryujinx.Tests.Cpu
public void SanityCheck(ulong a)
{
uint opcode = 0xD503201F; // NOP
- CpuThreadState threadState = SingleOpcode(opcode, x0: a);
+ ExecutionContext context = SingleOpcode(opcode, x0: a);
- Assert.That(threadState.X0, Is.EqualTo(a));
+ Assert.That(context.GetX(0), Is.EqualTo(a));
}
#endif
}
generated by cgit v1.2.3-70-g09d2 (git 2.48.1) at 2025-03-26 05:49:35 +0000