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authorgdkchan <gab.dark.100@gmail.com>2022-01-10 12:08:00 -0300
committerGitHub <noreply@github.com>2022-01-10 12:08:00 -0300
commit7f6b3d234a0dd82866e89930f05c520aca94946e (patch)
tree49459142740eed719d431d9dc9ae37b0ff472ee8 /Ryujinx.Graphics.Shader/Translation/Translator.cs
parent952c6e4d454082da900a447e6bd1deb272c150c2 (diff)
Implement IMUL, PCNT and CONT shader instructions, fix FFMA32I and HFMA32I (#2972)
* Implement IMUL shader instruction * Implement PCNT/CONT instruction and fix FFMA32I * Add HFMA232I to the table * Shader cache version bump * No Rc on Ffma32i
Diffstat (limited to 'Ryujinx.Graphics.Shader/Translation/Translator.cs')
-rw-r--r--Ryujinx.Graphics.Shader/Translation/Translator.cs2
1 files changed, 1 insertions, 1 deletions
diff --git a/Ryujinx.Graphics.Shader/Translation/Translator.cs b/Ryujinx.Graphics.Shader/Translation/Translator.cs
index cef25350..709b16db 100644
--- a/Ryujinx.Graphics.Shader/Translation/Translator.cs
+++ b/Ryujinx.Graphics.Shader/Translation/Translator.cs
@@ -295,7 +295,7 @@ namespace Ryujinx.Graphics.Shader.Translation
Operand predSkipLbl = null;
- if (op.Name == InstName.Sync || op.Name == InstName.Brk)
+ if (Decoder.IsPopBranch(op.Name))
{
// If the instruction is a SYNC or BRK instruction with only one
// possible target address, then the instruction is basically