diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2022-01-21 12:47:34 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-01-21 12:47:34 -0300 |
| commit | f0824fde9f511e9f6d1cda1f80549c93a5d6ce69 (patch) | |
| tree | 4e4a4c6a7e9be6bef72b9c45dd59be9aa48ec61d /ARMeilleure/Instructions | |
| parent | 7e967d796cf572377f21af3817a22755c5b01cb1 (diff) | |
Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)
* Add host CPU memory barriers for DMB/DSB and ordered load/store
* PPTC version bump
* Revert to old barrier order
Diffstat (limited to 'ARMeilleure/Instructions')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitMemoryEx.cs | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/ARMeilleure/Instructions/InstEmitMemoryEx.cs b/ARMeilleure/Instructions/InstEmitMemoryEx.cs index 522b2a47..88b9d2f0 100644 --- a/ARMeilleure/Instructions/InstEmitMemoryEx.cs +++ b/ARMeilleure/Instructions/InstEmitMemoryEx.cs @@ -167,9 +167,7 @@ namespace ARMeilleure.Instructions private static void EmitBarrier(ArmEmitterContext context) { - // Note: This barrier is most likely not necessary, and probably - // doesn't make any difference since we need to do a ton of stuff - // (software MMU emulation) to read or write anything anyway. + context.MemoryBarrier(); } } }
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