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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-07-17 06:21:40 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-17 14:21:40 +1000 |
| commit | 88619d71b8e4840218c68b712aa184098d2dbccf (patch) | |
| tree | 1994bfc8353c973c663f60d6f6f803cd7285723d /ARMeilleure/Instructions/InstName.cs | |
| parent | 9f6b24edfddf871320290463437b3f3cb7e29006 (diff) | |
CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)
Diffstat (limited to 'ARMeilleure/Instructions/InstName.cs')
| -rw-r--r-- | ARMeilleure/Instructions/InstName.cs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/ARMeilleure/Instructions/InstName.cs b/ARMeilleure/Instructions/InstName.cs index 69b5d3fc..28041874 100644 --- a/ARMeilleure/Instructions/InstName.cs +++ b/ARMeilleure/Instructions/InstName.cs @@ -545,6 +545,7 @@ namespace ARMeilleure.Instructions // FP & SIMD (AArch32) Vabs, Vadd, + Vaddw, Vand, Vbif, Vbit, @@ -611,6 +612,7 @@ namespace ARMeilleure.Instructions Vrsqrte, Vrsqrts, Vsub, + Vsubw, Vtbl, Vtrn, Vuzp, |