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authorWunk <wunkolo@gmail.com>2022-12-18 11:46:13 -0800
committerGitHub <noreply@github.com>2022-12-18 16:46:13 -0300
commit295fbd0542a93ac50e558054a3f0c8c64286b764 (patch)
tree0c5f631e2a53f10e42083f1623f5ff26926ef27d /ARMeilleure/Instructions/InstEmitSimdMove32.cs
parentd7310d7a1c3788ff931a5f46677386a07ceeaf62 (diff)
ARMeilleure: Add initial support for AVX512(EVEX encoding) (#3663)1.1.478
* ARMeilleure: Add AVX512{F,VL,DQ,BW} detection Add `UseAvx512Ortho` and `UseAvx512OrthoFloat` optimization flags as short-hands for `F+VL` and `F+VL+DQ`. * ARMeilleure: Add initial support for EVEX instruction encoding Does not implement rounding, or exception controls. * ARMeilleure: Add `X86Vpternlogd` Accelerates the vector-`Not` instruction. * ARMeilleure: Add check for `OSXSAVE` for AVX{2,512} * ARMeilleure: Add check for `XCR0` flags Add XCR0 register checks for AVX and AVX512F, following the guidelines from section 14.3 and 15.2 from the Intel Architecture Software Developer's Manual. * ARMeilleure: Increment InternalVersion * ARMeilleure: Remove redundant `ReProtect` and `Dispose`, formatting * ARMeilleure: Move XCR0 procedure to GetXcr0Eax * ARMeilleure: Add `XCR0` to `FeatureInfo` structure * ARMeilleure: Utilize `ReadOnlySpan` for Xcr0 assembly Avoids an additional allocation * ARMeilleure: Formatting fixes
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