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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-07-17 06:21:40 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-17 14:21:40 +1000 |
| commit | 88619d71b8e4840218c68b712aa184098d2dbccf (patch) | |
| tree | 1994bfc8353c973c663f60d6f6f803cd7285723d /ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs | |
| parent | 9f6b24edfddf871320290463437b3f3cb7e29006 (diff) | |
CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs index eb86ac9e..cc6e6edb 100644 --- a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs @@ -107,6 +107,13 @@ namespace ARMeilleure.Instructions } } + public static void Vaddw_I(ArmEmitterContext context) + { + OpCode32SimdRegWide op = (OpCode32SimdRegWide)context.CurrOp; + + EmitVectorBinaryWideOpI32(context, (op1, op2) => context.Add(op1, op2), !op.U); + } + public static void Vdup(ArmEmitterContext context) { OpCode32SimdDupGP op = (OpCode32SimdDupGP)context.CurrOp; @@ -1191,6 +1198,13 @@ namespace ARMeilleure.Instructions } } + public static void Vsubw_I(ArmEmitterContext context) + { + OpCode32SimdRegWide op = (OpCode32SimdRegWide)context.CurrOp; + + EmitVectorBinaryWideOpI32(context, (op1, op2) => context.Subtract(op1, op2), !op.U); + } + private static void EmitSse41MaxMinNumOpF32(ArmEmitterContext context, bool isMaxNum, bool scalar) { IOpCode32Simd op = (IOpCode32Simd)context.CurrOp; |