diff options
| author | merry <git@mary.rs> | 2022-02-22 22:11:28 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-22 19:11:28 -0300 |
| commit | 7b35ebc64a411e95e197bb36ad4b55c522c3703d (patch) | |
| tree | ce0db30b7c5f2111546cbe46121423ca7febf19f /ARMeilleure/Instructions/InstEmitAlu32.cs | |
| parent | 0a24aa6af26cc55c079e265a071a42569d28d2c0 (diff) | |
T32: Implement ALU (shifted register) instructions (#3135)1.1.53
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)
* OpCodeTable: Sort T32 list
* Tests: Rename RandomTestCase to PrecomputedThumbTestCase
* T32: Tests for AluRsImm instructions
* fix nit
* fix nit 2
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitAlu32.cs')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitAlu32.cs | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/ARMeilleure/Instructions/InstEmitAlu32.cs b/ARMeilleure/Instructions/InstEmitAlu32.cs index 1cbc0765..a612bdf2 100644 --- a/ARMeilleure/Instructions/InstEmitAlu32.cs +++ b/ARMeilleure/Instructions/InstEmitAlu32.cs @@ -244,6 +244,23 @@ namespace ARMeilleure.Instructions EmitAluStore(context, res); } + public static void Orn(ArmEmitterContext context) + { + IOpCode32Alu op = (IOpCode32Alu)context.CurrOp; + + Operand n = GetAluN(context); + Operand m = GetAluM(context); + + Operand res = context.BitwiseOr(n, context.BitwiseNot(m)); + + if (ShouldSetFlags(context)) + { + EmitNZFlagsCheck(context, res); + } + + EmitAluStore(context, res); + } + public static void Pkh(ArmEmitterContext context) { OpCode32AluRsImm op = (OpCode32AluRsImm)context.CurrOp; |