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| author | gdkchan <gab.dark.100@gmail.com> | 2022-09-09 22:09:11 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-09 22:09:11 -0300 |
| commit | c64524a240671cb3f8609e3454576e69e5948a60 (patch) | |
| tree | b02fe220963b33b4292adf7b4a5236dae6bc0b05 /ARMeilleure/Decoders/OpCodeT32ShiftReg.cs | |
| parent | db45688aa8d0e63d3ffbe50351722ef32f8360f8 (diff) | |
Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683)1.1.256
* Add ADD (zx imm12), NOP, MOV (register shifted), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions, fix LDRD, STRD, CBZ, CBNZ and BLX (reg)
* Bump PPTC version
Diffstat (limited to 'ARMeilleure/Decoders/OpCodeT32ShiftReg.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCodeT32ShiftReg.cs | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCodeT32ShiftReg.cs b/ARMeilleure/Decoders/OpCodeT32ShiftReg.cs new file mode 100644 index 00000000..36055975 --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32ShiftReg.cs @@ -0,0 +1,19 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32ShiftReg : OpCodeT32Alu, IOpCode32AluRsReg + { + public int Rm => Rn; + public int Rs { get; } + + public ShiftType ShiftType { get; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32ShiftReg(inst, address, opCode); + + public OpCodeT32ShiftReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rs = (opCode >> 0) & 0xf; + + ShiftType = (ShiftType)((opCode >> 21) & 3); + } + } +} |