diff options
| author | merry <git@mary.rs> | 2022-02-22 22:11:28 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-22 19:11:28 -0300 |
| commit | 7b35ebc64a411e95e197bb36ad4b55c522c3703d (patch) | |
| tree | ce0db30b7c5f2111546cbe46121423ca7febf19f /ARMeilleure/Decoders/OpCodeT32AluRsImm.cs | |
| parent | 0a24aa6af26cc55c079e265a071a42569d28d2c0 (diff) | |
T32: Implement ALU (shifted register) instructions (#3135)1.1.53
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)
* OpCodeTable: Sort T32 list
* Tests: Rename RandomTestCase to PrecomputedThumbTestCase
* T32: Tests for AluRsImm instructions
* fix nit
* fix nit 2
Diffstat (limited to 'ARMeilleure/Decoders/OpCodeT32AluRsImm.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCodeT32AluRsImm.cs | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs b/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs new file mode 100644 index 00000000..1c9ba7a2 --- /dev/null +++ b/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs @@ -0,0 +1,20 @@ +namespace ARMeilleure.Decoders +{ + class OpCodeT32AluRsImm : OpCodeT32Alu, IOpCode32AluRsImm + { + public int Rm { get; } + public int Immediate { get; } + + public ShiftType ShiftType { get; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluRsImm(inst, address, opCode); + + public OpCodeT32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Rm = (opCode >> 0) & 0xf; + Immediate = ((opCode >> 6) & 3) | ((opCode >> 10) & 0x1c); + + ShiftType = (ShiftType)((opCode >> 4) & 3); + } + } +}
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