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authormerry <git@mary.rs>2022-09-11 03:03:14 +0100
committerGitHub <noreply@github.com>2022-09-10 23:03:14 -0300
commit1529e6cf0dbd42f034b2809485810eb1c88ef7ff (patch)
treec9f5235c2b6f9e97e76489b5ca7f7d2d7c00688a /ARMeilleure/Decoders/OpCode32SimdSpecial.cs
parentf468db76028086a6645856383fecdf8180b04dd1 (diff)
T32: Add Vfp instructions (#3690)1.1.262
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdSpecial.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdSpecial.cs7
1 files changed, 5 insertions, 2 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdSpecial.cs b/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
index 1f1411f0..61a9f387 100644
--- a/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
@@ -5,10 +5,13 @@
public int Rt { get; }
public int Sreg { get; }
- public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode);
+ public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode, false);
+ public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode, true);
- public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+ public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
{
+ IsThumb = isThumb;
+
Rt = (opCode >> 12) & 0xf;
Sreg = (opCode >> 16) & 0xf;
}