diff options
| author | merry <git@mary.rs> | 2022-09-13 22:25:37 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-13 18:25:37 -0300 |
| commit | e05bf90af600f5c75a13a0b4113b7fc6a641ff6a (patch) | |
| tree | 87c8d482dcba254aa39221a406490d23378a3f87 /ARMeilleure/Decoders/OpCode32SimdRegWide.cs | |
| parent | 66f16f43921bdd6d0f706d09aa37166d374dec2e (diff) | |
T32: Implement Asimd instructions (#3692)1.1.268
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRegWide.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32SimdRegWide.cs | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs index 9a3993fa..fd2b3bf1 100644 --- a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs +++ b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs @@ -2,9 +2,10 @@ { class OpCode32SimdRegWide : OpCode32SimdReg { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode, false); + public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode, true); - public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb) { Q = false; RegisterSize = RegisterSize.Simd64; |