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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2020-10-13 22:41:33 +0200
committerGitHub <noreply@github.com>2020-10-13 22:41:33 +0200
commit04e330cc004add7550eef8361cd490fac99255e2 (patch)
tree3383f357cb61b5ba7b0b304d0d9d89c197c21050 /ARMeilleure/Decoders/OpCode32SimdRegWide.cs
parent329ba5b39b4402d96aea85f1e97dc35f70aadfab (diff)
Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). No test provided (i.e. draft). * Ptc InternalVersion = 1577
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRegWide.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdRegWide.cs2
1 files changed, 1 insertions, 1 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
index 55384b2b..93ef6949 100644
--- a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
@@ -1,6 +1,6 @@
namespace ARMeilleure.Decoders
{
- sealed class OpCode32SimdRegWide : OpCode32SimdReg
+ class OpCode32SimdRegWide : OpCode32SimdReg
{
public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{