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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-07-17 06:21:40 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-17 14:21:40 +1000 |
| commit | 88619d71b8e4840218c68b712aa184098d2dbccf (patch) | |
| tree | 1994bfc8353c973c663f60d6f6f803cd7285723d /ARMeilleure/Decoders/OpCode32SimdRegWide.cs | |
| parent | 9f6b24edfddf871320290463437b3f3cb7e29006 (diff) | |
CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRegWide.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32SimdRegWide.cs | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs new file mode 100644 index 00000000..55384b2b --- /dev/null +++ b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs @@ -0,0 +1,17 @@ +namespace ARMeilleure.Decoders +{ + sealed class OpCode32SimdRegWide : OpCode32SimdReg + { + public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + Q = false; + RegisterSize = RegisterSize.Simd64; + + // Subclasses have their own handling of Vx to account for before checking. + if (GetType() == typeof(OpCode32SimdRegWide) && DecoderHelper.VectorArgumentsInvalid(true, Vd, Vn)) + { + Instruction = InstDescriptor.Undefined; + } + } + } +} |