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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-10-13 22:41:33 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-13 22:41:33 +0200 |
| commit | 04e330cc004add7550eef8361cd490fac99255e2 (patch) | |
| tree | 3383f357cb61b5ba7b0b304d0d9d89c197c21050 /ARMeilleure/Decoders/OpCode32SimdRegLong.cs | |
| parent | 329ba5b39b4402d96aea85f1e97dc35f70aadfab (diff) | |
Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). (#1577)
* Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths).
No test provided (i.e. draft).
* Ptc InternalVersion = 1577
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRegLong.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32SimdRegLong.cs | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs index 24ae42d8..144824b3 100644 --- a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs +++ b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs @@ -8,7 +8,14 @@ { Q = false; RegisterSize = RegisterSize.Simd64; + Polynomial = ((opCode >> 9) & 0x1) != 0; + + // Subclasses have their own handling of Vx to account for before checking. + if (GetType() == typeof(OpCode32SimdRegLong) && DecoderHelper.VectorArgumentsInvalid(true, Vd)) + { + Instruction = InstDescriptor.Undefined; + } } } } |