aboutsummaryrefslogtreecommitdiff
path: root/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
diff options
context:
space:
mode:
authorgdkchan <gab.dark.100@gmail.com>2020-03-10 21:49:27 -0300
committerGitHub <noreply@github.com>2020-03-11 11:49:27 +1100
commitc26f3774bdbf3982149a3ea4c0f7abb4de869db7 (patch)
tree45805ff76e7a4f486d5132d39ec7f901f462adcb /ARMeilleure/Decoders/OpCode32SimdRegLong.cs
parent89ccec197ec9a5db2bb308ef3e9178910d1ab7a8 (diff)
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRegLong.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdRegLong.cs14
1 files changed, 14 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
new file mode 100644
index 00000000..24ae42d8
--- /dev/null
+++ b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
@@ -0,0 +1,14 @@
+namespace ARMeilleure.Decoders
+{
+ class OpCode32SimdRegLong : OpCode32SimdReg
+ {
+ public bool Polynomial { get; private set; }
+
+ public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+ {
+ Q = false;
+ RegisterSize = RegisterSize.Simd64;
+ Polynomial = ((opCode >> 9) & 0x1) != 0;
+ }
+ }
+}