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authorgdkchan <gab.dark.100@gmail.com>2020-03-10 21:49:27 -0300
committerGitHub <noreply@github.com>2020-03-11 11:49:27 +1100
commitc26f3774bdbf3982149a3ea4c0f7abb4de869db7 (patch)
tree45805ff76e7a4f486d5132d39ec7f901f462adcb /ARMeilleure/Decoders/OpCode32SimdRegElem.cs
parent89ccec197ec9a5db2bb308ef3e9178910d1ab7a8 (diff)
Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other fixes (#977)
* Implement VMULL, VMLSL, VQRSHRN, VQRSHRUN AArch32 instructions plus other fixes * Re-align opcode table * Re-enable undefined, use subclasses to fix checks * Add test and fix VRSHR instruction * PR feedback
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRegElem.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdRegElem.cs13
1 files changed, 10 insertions, 3 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
index 4bf15cca..c3b912b1 100644
--- a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
@@ -6,13 +6,20 @@
{
Q = ((opCode >> 24) & 0x1) != 0;
F = ((opCode >> 8) & 0x1) != 0;
- Size = ((opCode >> 20) & 0x3);
+ Size = (opCode >> 20) & 0x3;
RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;
- Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
+ if (Size == 1)
+ {
+ Vm = ((opCode >> 3) & 0x1) | ((opCode >> 4) & 0x2) | ((opCode << 2) & 0x1c);
+ }
+ else /* if (Size == 2) */
+ {
+ Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
+ }
- if (DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vn) || Size == 0 || (Size == 1 && F))
+ if (GetType() == typeof(OpCode32SimdRegElem) && DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vn) || Size == 0 || (Size == 1 && F))
{
Instruction = InstDescriptor.Undefined;
}