diff options
| author | merry <git@mary.rs> | 2022-09-13 22:25:37 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-13 18:25:37 -0300 |
| commit | e05bf90af600f5c75a13a0b4113b7fc6a641ff6a (patch) | |
| tree | 87c8d482dcba254aa39221a406490d23378a3f87 /ARMeilleure/Decoders/OpCode32SimdRegElem.cs | |
| parent | 66f16f43921bdd6d0f706d09aa37166d374dec2e (diff) | |
T32: Implement Asimd instructions (#3692)1.1.268
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRegElem.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32SimdRegElem.cs | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs index 0802a17b..173c5265 100644 --- a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs +++ b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs @@ -2,11 +2,12 @@ { class OpCode32SimdRegElem : OpCode32SimdReg { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode, false); + public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode, true); - public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb) { - Q = ((opCode >> 24) & 0x1) != 0; + Q = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0; F = ((opCode >> 8) & 0x1) != 0; Size = (opCode >> 20) & 0x3; |