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authorgdkchan <gab.dark.100@gmail.com>2022-09-13 03:24:09 -0300
committerGitHub <noreply@github.com>2022-09-13 08:24:09 +0200
commit729ff5337cab8d1fd4cc66d7792d410172f25f62 (patch)
tree65fe0eb59ecee1348da96865f8d9e5f648cd35d9 /ARMeilleure/Decoders/OpCode32SimdMemPair.cs
parent2492e7e808a3979ff54c5d28496d747e0a17fd5a (diff)
Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695)1.1.266
* Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 * PPTC version bump * PR feedback
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdMemPair.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdMemPair.cs7
1 files changed, 3 insertions, 4 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdMemPair.cs b/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
index 4cee05e8..2da0dea3 100644
--- a/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
@@ -1,11 +1,10 @@
using ARMeilleure.State;
-using System;
namespace ARMeilleure.Decoders
{
class OpCode32SimdMemPair : OpCode32, IOpCode32Simd
{
- private static int[] RegsMap =
+ private static int[] _regsMap =
{
1, 1, 4, 2,
1, 1, 3, 1,
@@ -40,9 +39,9 @@ namespace ARMeilleure.Decoders
WBack = Rm != RegisterAlias.Aarch32Pc;
RegisterIndex = Rm != RegisterAlias.Aarch32Pc && Rm != RegisterAlias.Aarch32Sp;
- Regs = RegsMap[(opCode >> 8) & 0xf];
+ Regs = _regsMap[(opCode >> 8) & 0xf];
- Increment = Math.Min(Regs, ((opCode >> 8) & 0x1) + 1);
+ Increment = ((opCode >> 8) & 0x1) + 1;
}
}
}