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| author | gdkchan <gab.dark.100@gmail.com> | 2020-03-10 02:17:30 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-10 16:17:30 +1100 |
| commit | 89ccec197ec9a5db2bb308ef3e9178910d1ab7a8 (patch) | |
| tree | 3f487a86d3495feefd904d4cd7195d9c798c008b /ARMeilleure/Decoders/OpCode32SimdLong.cs | |
| parent | 08c0e3829bc96932d386de18647bde2768fe26ed (diff) | |
Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)
* Implement VMOVL and VORR.I32 AArch32 SIMD instructions
* Rename <dt> to <size> on test description
* Rename Widen to Long and improve VMOVL implementation a bit
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdLong.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32SimdLong.cs | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdLong.cs b/ARMeilleure/Decoders/OpCode32SimdLong.cs new file mode 100644 index 00000000..c4b18683 --- /dev/null +++ b/ARMeilleure/Decoders/OpCode32SimdLong.cs @@ -0,0 +1,27 @@ +namespace ARMeilleure.Decoders +{ + class OpCode32SimdLong : OpCode32SimdBase + { + public bool U { get; private set; } + + public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + { + int imm3h = (opCode >> 19) & 0x7; + + // The value must be a power of 2, otherwise it is the encoding of another instruction. + switch (imm3h) + { + case 1: Size = 0; break; + case 2: Size = 1; break; + case 4: Size = 2; break; + } + + U = ((opCode >> 24) & 0x1) != 0; + + RegisterSize = RegisterSize.Simd64; + + Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf); + Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf); + } + } +} |