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| author | merry <git@mary.rs> | 2022-10-19 01:36:04 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-19 02:36:04 +0200 |
| commit | 8d41402fa603a2f00ccd08239d3b938fd60715a3 (patch) | |
| tree | 16f1c1f904ebf4a7b1f07c219f11a57f6f7c6494 /ARMeilleure/Decoders/OpCode32SimdCvtTB.cs | |
| parent | 5af8ce7c38d0b5c910a271ff4a43313850b49a59 (diff) | |
A32: Implement VCVTT, VCVTB (#3710)1.1.315
* A32: Implement VCVTT, VCVTB
* A32: F16C implementation of VCVTT/VCVTB
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdCvtTB.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32SimdCvtTB.cs | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs b/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs new file mode 100644 index 00000000..a95b32ab --- /dev/null +++ b/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs @@ -0,0 +1,44 @@ +namespace ARMeilleure.Decoders +{ + class OpCode32SimdCvtTB : OpCode32, IOpCode32Simd + { + public int Vd { get; } + public int Vm { get; } + public bool Op { get; } // Convert to Half / Convert from Half + public bool T { get; } // Top / Bottom + public int Size { get; } // Double / Single + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtTB(inst, address, opCode, false); + public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtTB(inst, address, opCode, true); + + public OpCode32SimdCvtTB(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode) + { + IsThumb = isThumb; + + Op = ((opCode >> 16) & 0x1) != 0; + T = ((opCode >> 7) & 0x1) != 0; + Size = ((opCode >> 8) & 0x1); + + RegisterSize = Size == 1 ? RegisterSize.Int64 : RegisterSize.Int32; + + if (Size == 1) + { + if (Op) + { + Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf); + Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e); + } + else + { + Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e); + Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf); + } + } + else + { + Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e); + Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e); + } + } + } +}
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