diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-08-13 07:34:02 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-13 02:34:02 -0300 |
| commit | 6938988427e7f96adcd8fe76fe5d0a19b014b2b2 (patch) | |
| tree | 39b049344e5d00b5f152b5354e7c8090ebf46c41 /ARMeilleure/Decoders/OpCode32SimdCvtFI.cs | |
| parent | 1ad9045c6b00a5c729c8c7d697f3da54ed177883 (diff) | |
Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471)
* Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests.
* Address PR feedback & Nit.
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdCvtFI.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32SimdCvtFI.cs | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs b/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs index aaedcb3c..b654a192 100644 --- a/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs +++ b/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs @@ -2,12 +2,20 @@ { class OpCode32SimdCvtFI : OpCode32SimdS { - public int Opc2 { get; private set; } - public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Opc2 = (opCode >> 16) & 0x7; Opc = (opCode >> 7) & 0x1; + + bool toInteger = (Opc2 & 0b100) != 0; + + if (toInteger) + { + Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e); + } + else + { + Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e); + } } } } |