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authorgdkchan <gab.dark.100@gmail.com>2020-02-29 17:51:55 -0300
committerGitHub <noreply@github.com>2020-03-01 07:51:55 +1100
commitfb0939f9b68d7fb83d863b22ef99af93452bb4bf (patch)
tree1be02b3674c8b94fee0cb12503bd00060810ccb5 /ARMeilleure/Decoders/OpCode32Sat.cs
parentb8ee5b15abc750e0484195633e6c4bb6e05eab6f (diff)
Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)
* Implement SMULWB, SMULWT, SMLAWB, SMLAWT, and add tests for some multiply instructions * Improve test descriptions * Rename SMULH to SMUL__ * Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions * Fix new tests * Replace AND 0xFFFF with 16-bits zero extension (more efficient)
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32Sat.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32Sat.cs22
1 files changed, 22 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCode32Sat.cs b/ARMeilleure/Decoders/OpCode32Sat.cs
new file mode 100644
index 00000000..b5ddab32
--- /dev/null
+++ b/ARMeilleure/Decoders/OpCode32Sat.cs
@@ -0,0 +1,22 @@
+namespace ARMeilleure.Decoders
+{
+ class OpCode32Sat : OpCode32
+ {
+ public int Rn { get; private set; }
+ public int Imm5 { get; private set; }
+ public int Rd { get; private set; }
+ public int SatImm { get; private set; }
+
+ public ShiftType ShiftType { get; private set; }
+
+ public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+ {
+ Rn = (opCode >> 0) & 0xf;
+ Imm5 = (opCode >> 7) & 0x1f;
+ Rd = (opCode >> 12) & 0xf;
+ SatImm = (opCode >> 16) & 0x1f;
+
+ ShiftType = (ShiftType)((opCode >> 5) & 2);
+ }
+ }
+} \ No newline at end of file