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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-11-18 19:35:54 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-11-18 19:35:54 +0100 |
| commit | 0679084f115b6838dec4d8c5e85044c33d4122d0 (patch) | |
| tree | 0d25ace42740e37d6bb2a8cd30fa92c5313d265a /ARMeilleure/CodeGen/X86/HardwareCapabilities.cs | |
| parent | eafee34feebd432151809df402f3f696e4d93d08 (diff) | |
CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650)
* net5.0
* CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Switch to .NET 5.0.
Nits.
Tests performed successfully in both debug and release mode (for all instructions involved).
* Address comment.
* Update appveyor.yml
* Revert "Update appveyor.yml"
This reverts commit 27cdd59e8b90e227e6924d9c162af26c00a89013.
* Remove Assembler CpuId.
* Update appveyor.yml
* Address comment.
Diffstat (limited to 'ARMeilleure/CodeGen/X86/HardwareCapabilities.cs')
| -rw-r--r-- | ARMeilleure/CodeGen/X86/HardwareCapabilities.cs | 62 |
1 files changed, 51 insertions, 11 deletions
diff --git a/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs b/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs index b622c65c..aa103e30 100644 --- a/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs +++ b/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs @@ -1,20 +1,60 @@ +using System; using System.Runtime.Intrinsics.X86; namespace ARMeilleure.CodeGen.X86 { static class HardwareCapabilities { - public static bool SupportsSse => Sse.IsSupported; - public static bool SupportsSse2 => Sse2.IsSupported; - public static bool SupportsSse3 => Sse3.IsSupported; - public static bool SupportsSsse3 => Ssse3.IsSupported; - public static bool SupportsSse41 => Sse41.IsSupported; - public static bool SupportsSse42 => Sse42.IsSupported; - public static bool SupportsPclmulqdq => Pclmulqdq.IsSupported; - public static bool SupportsFma => Fma.IsSupported; - public static bool SupportsPopcnt => Popcnt.IsSupported; - public static bool SupportsAesni => Aes.IsSupported; - public static bool SupportsAvx => Avx.IsSupported; + static HardwareCapabilities() + { + if (!X86Base.IsSupported) + { + return; + } + + (_, _, int ecx, int edx) = X86Base.CpuId(0x00000001, 0x00000000); + + FeatureInfoEdx = (FeatureFlagsEdx)edx; + FeatureInfoEcx = (FeatureFlagsEcx)ecx; + } + + [Flags] + public enum FeatureFlagsEdx + { + Sse = 1 << 25, + Sse2 = 1 << 26 + } + + [Flags] + public enum FeatureFlagsEcx + { + Sse3 = 1 << 0, + Pclmulqdq = 1 << 1, + Ssse3 = 1 << 9, + Fma = 1 << 12, + Sse41 = 1 << 19, + Sse42 = 1 << 20, + Popcnt = 1 << 23, + Aes = 1 << 25, + Avx = 1 << 28, + F16c = 1 << 29 + } + + public static FeatureFlagsEdx FeatureInfoEdx { get; } + public static FeatureFlagsEcx FeatureInfoEcx { get; } + + public static bool SupportsSse => FeatureInfoEdx.HasFlag(FeatureFlagsEdx.Sse); + public static bool SupportsSse2 => FeatureInfoEdx.HasFlag(FeatureFlagsEdx.Sse2); + public static bool SupportsSse3 => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.Sse3); + public static bool SupportsPclmulqdq => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.Pclmulqdq); + public static bool SupportsSsse3 => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.Ssse3); + public static bool SupportsFma => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.Fma); + public static bool SupportsSse41 => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.Sse41); + public static bool SupportsSse42 => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.Sse42); + public static bool SupportsPopcnt => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.Popcnt); + public static bool SupportsAesni => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.Aes); + public static bool SupportsAvx => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.Avx); + public static bool SupportsF16c => FeatureInfoEcx.HasFlag(FeatureFlagsEcx.F16c); public static bool ForceLegacySse { get; set; } |