diff options
| author | sharmander <saldabain.dev@gmail.com> | 2020-12-03 14:20:02 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-03 20:20:02 +0100 |
| commit | b479a43939b77b7f6d67f103f1fdc9126466f780 (patch) | |
| tree | b1655fc5a2e40e6bb4d93179d4d1e0f70db44eed /ARMeilleure/CodeGen/X86/CodeGenerator.cs | |
| parent | c00d39b675d0ebf7ebf5be1135addbbee2510d93 (diff) | |
CPU: Implement VFNMS.F32/64 (#1758)
* Add necessary methods / op-code
* Enable Support for FMA Instruction Set
* Add Intrinsics / Assembly Opcodes for VFMSUB231XX.
* Add X86 Instructions for VFMSUB231XX
* Implement VFNMS
* Implement VFNMS Tests
* Add special cases for FMA instructions.
* Update PPTC Version
* Remove unused Op
* Move Check into Assert / Cleanup
* Rename and cleanup
* Whitespace
* Whitespace / Rename
* Re-sort
* Address final requests
* Implement VFMA.F64
* Simplify switch
* Simplify FMA Instructions into their own IntrinsicType.
* Remove whitespace
* Fix indentation
* Change tests for Vfnms -- disable inf / nan
* Move args up, not description ;)
* Undo vfma
* Completely remove vfms code.,
* Fix order of instruction in assembler
Diffstat (limited to 'ARMeilleure/CodeGen/X86/CodeGenerator.cs')
| -rw-r--r-- | ARMeilleure/CodeGen/X86/CodeGenerator.cs | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/ARMeilleure/CodeGen/X86/CodeGenerator.cs b/ARMeilleure/CodeGen/X86/CodeGenerator.cs index c9acd945..83ff136a 100644 --- a/ARMeilleure/CodeGen/X86/CodeGenerator.cs +++ b/ARMeilleure/CodeGen/X86/CodeGenerator.cs @@ -406,12 +406,9 @@ namespace ARMeilleure.CodeGen.X86 else { EnsureSameReg(dest, src1); - Debug.Assert(src3.GetRegister().Index == 0); - context.Assembler.WriteInstruction(info.Inst, dest, src1, src2); } - break; } @@ -435,6 +432,23 @@ namespace ARMeilleure.CodeGen.X86 break; } + + case IntrinsicType.Fma: + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + Operand src3 = operation.GetSource(2); + + EnsureSameType(dest, src1, src2, src3); + EnsureSameReg(dest, src1); + Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(HardwareCapabilities.SupportsVexEncoding); + + context.Assembler.WriteInstruction(info.Inst, dest, src2, src3); + + break; + } } } else |