diff options
| author | merry <git@mary.rs> | 2022-02-11 20:51:03 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-11 17:51:03 -0300 |
| commit | ce71f9144e1575c432bb009755f01466cd685fbf (patch) | |
| tree | 3f8355b47553388367ec4f0d478e1a70d37fd493 | |
| parent | f861f0bca2767f74478bc444a7a057d05cc96638 (diff) | |
InstEmitMemory32: Literal loads always have word-aligned PC (#3104)1.1.26
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitHelper.cs | 14 | ||||
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitMemory32.cs | 2 |
2 files changed, 15 insertions, 1 deletions
diff --git a/ARMeilleure/Instructions/InstEmitHelper.cs b/ARMeilleure/Instructions/InstEmitHelper.cs index 0479c380..d1b9de84 100644 --- a/ARMeilleure/Instructions/InstEmitHelper.cs +++ b/ARMeilleure/Instructions/InstEmitHelper.cs @@ -47,6 +47,20 @@ namespace ARMeilleure.Instructions } } + public static Operand GetIntA32AlignedPC(ArmEmitterContext context, int regIndex) + { + if (regIndex == RegisterAlias.Aarch32Pc) + { + OpCode32 op = (OpCode32)context.CurrOp; + + return Const((int)(op.GetPc() & 0xfffffffc)); + } + else + { + return Register(GetRegisterAlias(context.Mode, regIndex), RegisterType.Integer, OperandType.I32); + } + } + public static Operand GetVecA32(int regIndex) { return Register(regIndex, RegisterType.Vector, OperandType.V128); diff --git a/ARMeilleure/Instructions/InstEmitMemory32.cs b/ARMeilleure/Instructions/InstEmitMemory32.cs index 64189134..af9eaf1a 100644 --- a/ARMeilleure/Instructions/InstEmitMemory32.cs +++ b/ARMeilleure/Instructions/InstEmitMemory32.cs @@ -153,7 +153,7 @@ namespace ARMeilleure.Instructions { OpCode32Mem op = (OpCode32Mem)context.CurrOp; - Operand n = context.Copy(GetIntA32(context, op.Rn)); + Operand n = context.Copy(GetIntA32AlignedPC(context, op.Rn)); Operand m = GetMemM(context, setCarry: false); Operand temp = default; |